Hub/router for communication between cores using cartesian coordinates

• US 20030154324A1
• Filed: 02/13/2002
• Published: 08/14/2003
• Est. Priority Date: 02/13/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ventrone, Sebastian, Harding, W. Riyon
• Granted Patent: US 7,085,913 B2
• Time in Patent Office: Days
• US Class Current: 710/1
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)

Abstract

A method and structure for an integrated circuit is disclosed. The invention includes a plurality of logic cores, a plurality of local hubs connected to said logic cores, and a plurality of global hubs connected to said local hubs. The local hubs and the global hubs transfer data between the logic cores.

Claims

1. An integrated circuit comprising:

a plurality of logic cores;

a plurality of local hubs connected to said logic cores; and

a plurality of global hubs connected to said local hubs, wherein said local hubs and said global hubs transfer data between said logic cores.

2. The integrated circuit in claim 1, further comprising:

first data paths connecting said local hubs to said logic cores; and

second data paths connecting said local hubs to said global hubs and said global hubs to each other.

3. The integrated circuit in claim 1, wherein said local hubs and said global hubs include buffers for storing said data when a data transmission cannot be completed within a given clock cycle.

4. The integrated circuit in claim 1, wherein, at least one of said local hubs and said global hubs includes a processor that selects a shortest path to a destination hub.

5. The integrated circuit in claim 4, wherein at least one of said local hubs and said global hubs includes a processor that selects an alternate path if said shortest path is blocked.

6. The integrated circuit in claim 1, wherein each of said local hubs connects to a plurality of said logic cores and each of said global hubs connects to a plurality of said local hubs.

7. The integrated circuit in claim 1, wherein a concentration of said hubs within said circuit is asymmetrical.

8. The integrated circuit in claim 1, wherein more hubs are located in areas of high data traffic volume than in areas of low data traffic volume.

9. An integrated circuit comprising:

a plurality of logic cores;

a plurality of local hubs connected to said logic cores;

a plurality of global hubs connected to said local hubs;

first data paths connecting said local hubs to said logic cores; and

second data paths connecting said local hubs to said global hubs and said global hubs to each other,

wherein said local hubs and said global hubs transfer data between said logic cores, and

wherein said local data paths and said global data paths are independent of one another.

10. The integrated circuit in claim 9, wherein said local hubs and said global hubs include buffers for storing said data when a data transmission cannot be completed within a given clock cycle.

11. The integrated circuit in claim 9, wherein at least one of said local hubs and said global hubs includes a processor that selects a shortest path to a destination hub.

12. The integrated circuit in claim 11, wherein at least one of said local hubs and said global hubs include a processor that selects an alternate path if said shortest path is blocked.

13. The integrated circuit in claim 9, wherein each of said local hubs connects to a plurality of said logic cores and each of said global hubs connects to a plurality of said local hubs.

14. The integrated circuit in claim 9, wherein a concentration of said hubs within said circuit is asymmetrical.

15. The integrated circuit in claim 9, wherein more hubs are located in areas of high data traffic volume than in areas of low data traffic volume.

16. A method of transferring data between logic cores in an integrated circuit, said method comprising:

transferring data from a sending logic core to a first local hub;

transferring said data from said first in local hub to a first global hub;

transferring said data from said first global hub to a second global hub;

transferring said data from said second global hub to be a second local hub; and

transferring said data from said second local hub to a destination logic core.

17. The method in claim 16, wherein said data identifies said destination logic core using a destination address and each of said first local hub, said first global hub, said second global hub, and said second local hub transfer said data based upon said destination address.

18. The method in claim 16, wherein said data is transferred to and from said first local hub and said second local hub over local data paths;

and

wherein said data is transferred between said first global hub and said second global hub over global data paths.

19. The method in claim 16, wherein each of said transferring processes includes a process of selecting a primary data path that comprises a shortest distance to said destination logic core.

20. The method in claim 19, wherein said shortest distance is calculated according to a Cartesian Coordinate system.

21. The method in claim 19, further comprising selecting a shortest alternative data path when said primary data path is busy, wherein said shortest alternative data path comprises a next shortest distance to said destination logic core.

22. A method of designing communication pathways between logic cores within an integrated circuit, said method comprising:

connecting a plurality of local hubs to said logic cores; and

connecting a plurality of global hubs to said local hubs.

23. The method in claim 22, further comprising positioning said local hubs and said global hubs according to traffic requirements of said integrated circuit, such that a pattern of said local hubs and said global hubs is asymmetric across said integrated circuit.

24. The method in claim 23, wherein said positioning comprises:

performing an initial placement of said local hubs and said global hubs on said integrated circuit; and

adding and removing said local hubs and said global hubs according to said traffic requirements.

25. The method in claim 22, further comprising:

forming local data paths to connect said local hubs to each other, to said logic cores, and to said global hubs; and

forming global data paths to connect said global hubs to each other, and to said local hubs.

26. The method in claim 25, wherein said forming of said local data paths connects each of said local hubs to all other local hubs;

and

wherein said forming of said global data paths connects each of said global hubs to all other global hubs.

27. The method in claim 25, wherein said forming of said local data paths connects each of said local hubs to less than all other local hubs;

and

wherein said forming of said global data paths connects each of said global hubs to less than all other global hubs.

28. The method in claim 22, wherein a plurality of said logic cores are connected to each of said local hubs, and wherein a plurality of said local hubs are connected to each of said global hubs.