Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

• US 20030154433A1
• Filed: 01/10/2003
• Published: 08/14/2003
• Est. Priority Date: 01/16/2002
• Status: Active Grant

• Current Assignee: Syntest Technologies Incorporated
• Original Assignee: Syntest Technologies Incorporated
• Inventors: Yeh, Ta-Chia, Wang, Hsin-Po, Wang, Laung-Terng, Wen, Xiaoqing, Lin, Meng-Chyi, Lin, Shyh-Horng, Abdel-Hafez, Khader S., Tsai, Sen-Wei
• Granted Patent: US 7,552,373 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Claims

1. A broadcaster having broadcast scan inputs that accepts virtual scan patterns via said broadcast scan inputs for generating broadcast scan patterns to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, said broadcaster comprising:

a) a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above.

2. The broadcaster of claim 1, further comprising using a first scan connector to merge two selected scan chains into one long scan chain, wherein said first scan connector is a buffer, an inverter, or a lockup element comprising an inverter and a memory element, such as D flip-flop or D latch.

3. The broadcaster of claim 1, further comprising inserting a second scan connector into a selected scan chain to reduce or eliminate the interdependency of said selected scan chain on other selected scan chains, wherein said second scan connector further comprises one or more spare scan cells.

4. The broadcaster of claim 1, further comprising transmitting said virtual scan patterns to said broadcast scan inputs of said broadcaster and transmitting said broadcast scan patterns generated by said broadcaster to selected scan data inputs of said scan chains in said scan-based integrated circuit.

5. The broadcaster of claim 1, further comprising storing said virtual scan patterns in an ATE (automatic test equipment), transmitting said virtual scan patterns to said broadcaster and transmitting said broadcast scan patterns generated by said broadcaster to said scan-based integrated circuit for test manufacturing faults, including stuck-at faults, transition faults, path-delay faults, IDDQ (IDD quiescent current) faults, and bridging faults, within said scan-based integrated circuit.

6. The broadcaster of claim 1, further comprising placing said broadcaster selectively inside or external to said scan-based integrated circuit.

7. A broadcaster having broadcast scan inputs that accepts virtual scan patterns via said broadcast scan inputs as well as virtual scan inputs for generating broadcast scan patterns to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, said broadcaster comprising:

a) a virtual scan controller for controlling the operation of said broadcaster during each shift cycle or between test sessions; and

b) a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above.

8. The broadcaster of claim 7, further comprising using a first scan connector to merge two selected scan chains into one long scan chain, wherein said first scan connector is a buffer, an inverter, or a lockup element comprising an inverter and a memory element, such as D flip-flop or D latch.

9. The broadcaster of claim 7, further comprising inserting a second scan connector into a selected scan chain to reduce or eliminate the interdependency of said selected scan chain on other selected scan chains, wherein said second scan connector further comprises one or more spare scan cells.

10. The broadcaster of claim 7, further comprising using a third scan connector to split a selected scan chain to two or more short scan chains or merge a plurality of selected scan chains into one long scan chain, wherein said third scan connector further comprises one or more multiplexers and wherein said multiplexers are controlled by said virtual scan controller.

11. The broadcaster of claim 7, wherein said virtual scan controller further comprises one or more buffers or inverters.

12. The broadcaster of claim 7, wherein said virtual scan controller is a decoder.

13. The broadcaster of claim 7, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

14. The broadcaster of claim 13, wherein said virtual scan controller is a shift register.

15. The broadcaster of claim 7, further comprising transmitting said virtual scan patterns to said virtual scan inputs and said broadcast scan inputs of said broadcaster and transmitting said broadcast scan patterns generated by said broadcaster to selected scan data inputs of said scan chains in said scan-based integrated circuit.

16. The broadcaster of claim 7, further comprising storing said virtual scan patterns in an ATE (automatic test equipment), transmitting said virtual scan patterns to said broadcaster and transmitting said broadcast scan patterns generated by said broadcaster to said scan-based integrated circuit for test manufacturing faults, including stuck-at faults, transition faults, path-delay faults, IDDQ (IDD quiescent current) faults, and bridging faults, within said scan-based integrated circuit.

17. The broadcaster of claim 7, further comprising placing said broadcaster selectively inside or external to said scan-based integrated circuit.

18. A system that accepts virtual scan patterns stored in an ATE (automatic test equipment) for generating broadcast scan patterns to test a scan-based integrated circuit, a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, said system comprising:

a) placing said broadcaster between said ATE and said scan-based integrated circuit;

b) transmitting a new said virtual scan pattern stored in said ATE to said broadcaster for generating said broadcast scan pattern to test manufacturing faults in said scan-based integrated circuit;

c) comparing the test response of said scan-based integrated circuit with the expected test response; and

d) repeating steps (b) to (c) until predetermined limiting criteria are met.

19. The system of claim 18, wherein said broadcaster is a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above.

20. The system of claim 19, wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said combinational logic network to selected scan chain inputs in said scan-based integrated circuit, wherein said plurality of scan connectors include one or more buffers, inverters, lockup elements each comprising an inverter and a memory element such as D flip-flop or D latch, spare scan cells, multiplexers, or any combination of the above.

21. The system of claim 19, wherein said broadcaster further comprises using a virtual scan controller to control said combinational logic network, wherein said virtual scan controller controls the operation of said broadcaster during each shift cycle or between test sessions.

22. The system of claim 21, wherein said virtual scan controller further comprises one or more buffers or inverters.

23. The system of claim 21, wherein said virtual scan controller is a decoder.

24. The system of claim 21, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

25. The system of claim 24, wherein said virtual scan controller is a shift register.

26. The system of claim 18, wherein said broadcaster is selectively placed within said scan-based integrated circuit or inside said ATE.

27. The system of claim 18, wherein said comparing the test response of said scan-based integrated circuit with the expected test response further comprises using a compactor for compacting selected outputs of said integrated circuit for comparison, wherein said compactor is selectively modeled using simulation in said ATE or placed between said scan-based integrated circuit and said ATE.

28. The system of claim 27, wherein said compactor is selectively an XOR network or a multiple-input signature register (MISR), wherein said multiple-input signature register (MISR) further comprises a plurality of XOR gates and a plurality of memory elements, such as D flip-flops or D latches.

29. The system of claim 27, wherein said compactor further comprises using a mask network to enable or disable testing or diagnosis of selected scan cells in selected scan chains, wherein said mask network includes one or more AND gates.

30. The system of claim 27, wherein said compactor is selectively placed within said scan-based integrated circuit or inside said ATE.

31. The system of claim 18, wherein said broadcast scan patterns are chosen to test said manufacturing faults, including stuck-at faults, transition faults, path-delay faults, IDDQ (IDD quiescent current) faults, and bridging faults, in said scan-based integrated circuit.

32. A system that accepts virtual scan patterns stored in an ATE (automatic test equipment) for generating broadcast scan patterns to test a scan-based integrated circuit, a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, said system comprising:

a) using simulation, modeling said broadcaster in said ATE;

b) applying a new said virtual scan pattern stored in said ATE to generate said broadcast scan pattern using the simulated broadcaster model;

c) transmitting said broadcast scan pattern generated by said broadcaster in said ATE to said scan chains in said scan-based integrated circuit for testing manufacturing faults in said scan-based integrated circuit;

d) comparing the test response of said scan-based integrated circuit with the expected test response; and

e) repeating steps (b) to (d) until predetermined limiting criteria are met.

33. The system of claim 32, wherein said broadcaster is a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above.

34. The system of claim 33, wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said combinational logic network to selected scan chain inputs in said scan-based integrated circuit, wherein said plurality of scan connectors include one or more buffers, inverters, lockup elements each comprising an inverter and a memory element such as D flip-flop or D latch, spare scan cells, multiplexers, or any combination of the above.

35. The system of claim 33, wherein said broadcaster further comprises using a virtual scan controller to control said combinational logic network, wherein said virtual scan controller controls the operation of said broadcaster during each shift cycle or between test sessions.

36. The system of claim 35, wherein said virtual scan controller further comprises one or more buffers or inverters.

37. The system of claim 35, wherein said virtual scan controller is a decoder.

38. The system of claim 35, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

39. The system of claim 38, wherein said virtual scan controller is a shift register.

40. The system of claim 32, wherein said comparing the test response of said scan-based integrated circuit with the expected test response further comprises using a compactor for compacting selected outputs of said integrated circuit for comparison, wherein said compactor is selectively modeled using simulation in said ATE or placed between said scan-based integrated circuit and said ATE.

41. The system of claim 40, wherein said compactor is selectively an XOR network or a multiple-input signature register (MISR), wherein said multiple-input signature register (MISR) further comprises a plurality of XOR gates and a plurality of memory elements, such as D flip-flops or D latches.

42. The system of claim 40, wherein said compactor further comprises using a mask network to enable or disable testing or diagnosis of selected scan cells in selected scan chains, wherein said mask network includes one or more AND gates.

43. The system of claim 40, wherein said compactor is selectively placed within said scan-based integrated circuit or inside said ATE.

44. The system of claim 32, wherein said broadcast scan patterns are chosen to test said manufacturing faults, including stuck-at faults, transition faults, path-delay faults, IDDQ (IDD quiescent current) faults, and bridging faults, in said scan-based integrated circuit.

45. A method that reorders scan cells for generating broadcast scan patterns to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to a broadcaster, said method comprising the steps of:

a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or gate-level that represents said scan-based integrated circuit into a sequential circuit model;

b) establishing an original scan order and a set of scan order constraints on selected scan chains based on the design of said broadcaster;

c) transforming said sequential circuit model into an equivalent combinational circuit model;

d) performing an input-cone analysis on selected scan cells in said selected scan chains according to said original scan order and said scan order constraints; and

e) generating an optimal scan order to minimize the inter-dependency of said selected scan cells on said selected scan chains to be positioned on the same shift cycle.

46. The method of claim 45, further comprising reordering said selected scan cells in said selected scan chains according to said optimal scan order.

47. The method of claim 46, further comprising inserting one or more spare scan cells into a said selected scan chain to further minimize or eliminate the inter-dependency of said selected scan chain on other selected scan chains.

48. A method that generates broadcast scan patterns to test a scan-based integrated circuit through a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, said method comprising the steps of:

a) compiling the HDL (hardware description language) code modeled at gate-level that represents said scan-based integrated circuit into a sequential circuit model;

b) establishing a set of input constraints on selected scan cells based on the predetermined values to be assigned on said broadcaster during each shift cycle or between test sessions;

c) transforming said sequential circuit model into an equivalent combinational circuit model;

d) generating said broadcast scan patterns according to said set of input constraints; and

e) re-assigning a new set of input constraints and repeating step (d) until a predetermined limiting criteria are met.

49. The method of claim 48, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing random-pattern fault simulation on said equivalent combinational circuit model using a selected set of random patterns as said broadcast scan patterns.

50. The method of claim 48, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing combinational ATPG (automatic test pattern generation) on said equivalent combinational circuit model to generate said broadcast scan patterns.

51. The method of claim 48, further comprising finding an optimal scan order to minimize the inter-dependency of selected scan cells in a selected scan chain on other selected scan cells in other selected scan chains to be positioned on the same shift cycle.

52. The method of claim 51, wherein said finding an optimal scan order further comprises reordering said selected scan cells in said selected scan chains according to said optimal scan order.

53. The method of claim 52, wherein said finding an optimal scan order further comprises inserting one or more spare scan cells into a said selected scan chain to further minimize or eliminate the inter-dependency of said selected scan chain on other selected scan chains.

54. The method of claim 48, further comprising generating HDL test benches as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster and said scan-based integrated circuit using simulation methods.

55. The method of claim 48, further comprising generating ATE (automatic test equipment) test programs as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster and said scan-based integrated circuit in said ATE.

56. The method of claim 48, wherein said broadcaster is a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above.

57. The method of claim 56, wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said combinational logic network to selected scan chain inputs in said scan-based integrated circuit, wherein said plurality of scan connectors include one or more buffers, inverters, lockup elements each comprising an inverter and a memory element such as D flip-flop or D latch, spare scan cells, multiplexers, or any combination of the above.

58. The method of claim 56, wherein said broadcaster further comprises using a virtual scan controller to control said combinational logic network, wherein said virtual scan controller controls the operation of said broadcaster during each shift cycle or between test sessions.

59. The method of claim 58, wherein said virtual scan controller further comprises one or more buffers or inverters.

60. The method of claim 58, wherein said virtual scan controller is a decoder.

61. The method of claim 58, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

62. The method of claim 61, wherein said virtual scan controller is a shift register.

63. The method of claim 48, wherein said broadcast scan patterns are chosen to test manufacturing faults, including stuck-at faults, transition faults, path-delay faults, IDDQ (IDD quiescent current) faults, and bridging faults, in said scan-based integrated circuit.

64. A computer-readable memory having computer-readable program code embodied therein for causing a computer system to perform a method that generates broadcast scan patterns to test a scan-based integrated circuit through a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, said method comprising the steps of:

a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or gate-level that represents said scan-based integrated circuit into a sequential circuit model;

b) establishing a set of input constraints on selected scan cells based on the predetermined values to be assigned on said broadcaster during each shift cycle or between test sessions;

c) transforming said sequential circuit model into an equivalent combinational circuit model;

d) generating said broadcast scan patterns according to said set of input constraints; and

e) re-assigning a new set of input constraints and repeating step (d) until predetermined limiting criteria are met.

65. The computer-readable memory of claim 64, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing random-pattern fault simulation on said equivalent combinational circuit model using a selected set of random patterns as said broadcast scan patterns.

66. The computer-readable memory of claim 64, wherein said generating said broadcast scan patterns according to said set of inplut constraints further comprises performing combinational ATPG (automatic test pattern generation) on said equivalent combinational circuit model to generate said broadcast scan patterns.

67. The computer-readable memory of claim 64, further comprising finding an optimal scan order to minimize the inter-dependency of selected scan cells in a selected scan chain on other selected scan cells in other selected scan chains to be positioned on the same shift cycle.

68. The computer-readable memory of claim 67, wherein said finding an optimal scan order further comprises reordering said selected scan cells in said selected scan chains according to said optimal scan order.

69. The computer-readable memory of claim 68, wherein said finding an optimal scan order further comprises inserting one or more spare scan cells into a said selected scan chain to further minimize or eliminate the interdependency of said selected scan chain on other selected scan chains.

70. The computer-readable memory of claim 64, further comprising generating HDL test benches as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster and said scan-based integrated circuit using simulation methods.

71. The computer-readable memory of claim 64, further comprising generating ATE (automatic test equipment) test programs as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster and said scan-based integrated circuit in said ATE.

72. The computer-readable memory of claim 64, wherein said broadcaster is a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above.

73. The computer-readable memory of claim 72, wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said combinational logic network to selected scan chain inputs in said scan-based integrated circuit, wherein said plurality of scan connectors include one or more buffers, inverters, lockup elements each comprising an inverter and a memory element such as D flip-flop or D latch, spare scan cells, multiplexers, or any combination of the above.

74. The computer-readable memory of claim 72, wherein said broadcaster further comprises using a virtual scan controller to control said combinational logic network, wherein said virtual scan controller controls the operation of said broadcaster during each shift cycle or between test sessions.

75. The computer-readable memory of claim 74, wherein said virtual scan controller further comprises one or more buffers or inverters.

76. The computer-readable memory of claim 74, wherein said virtual scan controller is a decoder.

77. The computer-readable memory of claim 74, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

78. The computer-readable memory of claim 77, wherein said virtual scan controller is a shift register.

79. The computer-readable memory of claim 64, wherein said broadcast scan patterns are chosen to test manufacturing faults, including stuck-at faults, transition faults, path-delay faults, IDDQ (IDD quiescent current) faults, and bridging faults, in said scan-based integrated circuit.

80. An electronic design automation system comprising:

a processor;

a bus coupled to said processor; and

a computer-readable memory coupled to said bus and having computer-readable program code stored therein for causing said electronic design automation system to perform a method that generates broadcast scan patterns to test a scan-based integrated circuit through a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, said method comprising the steps of;

a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or gate-level that represents said scan-based integrated circuit into a sequential circuit model;

b) establishing a set of input constraints on selected scan cells based on the predetermined values to be assigned on said broadcaster during each shift cycle or between test sessions;

c) transforming said sequential circuit model into an equivalent combinational circuit model;

d) generating said broadcast scan patterns according to said set of input constraints; and

e) re-assigning a new set of input constraints and repeating step (d) until predetermined limiting criteria are met.

81. The system of claim 80, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing random-pattern fault simulation on said equivalent combinational circuit model using a selected set of random patterns as said broadcast scan patterns.

82. The system of claim 80, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing combinational ATPG (automatic test pattern generation) on said equivalent combinational circuit model to generate said broadcast scan patterns.

83. The system of claim 80, further comprising finding an optimal scan order to minimize the inter-dependency of selected scan cells in a selected scan chain on other selected scan cells in other selected scan chains to be positioned on the same shift cycle.

84. The system of claim 83, wherein said finding an optimal scan order further comprises reordering said selected scan cells in said selected scan chains according to said optimal scan order.

85. The system of claim 84, wherein said finding an optimal scan order further comprises inserting one or more spare scan cells into a said selected scan chain to further minimize or eliminate the inter-dependency of said selected scan chain on other selected scan chains.

86. The system of claim 80, further comprising generating HDL test benches as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster and said scan-based integrated circuit using simulation methods.

87. The system of claim 80, further comprising generating ATE (automatic test equipment) test programs as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster and said scan-based integrated circuit in said ATE.

88. The system of claim 80, wherein said broadcaster is a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above.

89. The system of claim 88, wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said combinational logic network to selected scan chain inputs in said scan-based integrated circuit, wherein said plurality of scan connectors include one or more buffers, inverters, lockup elements each comprising an inverter and a memory element such as D flip-flop or D latch, spare scan cells, multiplexers, or any combination of the above.

90. The system of claim 88, wherein said broadcaster further comprises using a virtual scan controller to control said combinational logic network, wherein said virtual scan controller controls the operation of said broadcaster during each shift cycle or between test sessions.

91. The system of claim 90, wherein said virtual scan controller further comprises one or more buffers or inverters.

92. The system of claim 90, wherein said virtual scan controller is a decoder.

93. The system of claim 90, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

94. The system of claim 93, wherein said virtual scan controller is a shift register.

95. The system of claim 80, wherein said broadcast scan patterns are chosen to test manufacturing faults, including stuck-at faults, transition faults, path-delay faults, IDDQ (IDD quiescent current) faults, and bridging faults, in said scan-based integrated circuit.

96. A method that synthesizes a broadcaster and a compactor to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chain inputs coupled to the broadcaster and the scan chain outputs coupled to the compactor, said method comprising the steps of:

a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or gate-level that represents said scan-based integrated circuit into a sequential circuit model;

b) establishing constraints on said broadcaster, said compactor, and for stitching;

c) synthesizing said broadcaster according to said constraints specified on said broadcaster;

d) synthesizing said compactor according to said constraints specified on said compactor;

e) stitching said broadcaster and said compactor on said sequential circuit model according to said constraints specified for stitching; and

f) generating synthesized HDL code modeled at RTL or gate-level.

97. The method of claim 96, wherein said broadcaster further comprises removing selected scan cells from selected scan chains and re-stitching said selected scan cells in said selected scan chains according to said constraints specified on said broadcaster.

98. The method of claim 96, wherein said broadcaster is a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above.

99. The system of claim 98, wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said combinational logic network to selected scan chain inputs in said scan-based integrated circuit, wherein said plurality of scan connectors include one or more buffers, inverters, lockup elements each comprising an inverter and a memory element such as D flip-flop or D latch, spare scan cells, multiplexers, or any combination of the above.

100. The system of claim 98, wherein said broadcaster further comprises using a virtual scan controller to control said combinational logic network, wherein said virtual scan controller controls the operation of said broadcaster during each shift cycle or between test sessions.

101. The method of claim 100, wherein said virtual scan controller further comprises one or more buffers or inverters.

102. The method of claim 100, wherein said virtual scan controller is a decoder.

103. The method of claim 100, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

104. The method of claim 103, wherein said virtual scan controller is a shift register.

105. The method of claim 96, wherein said broadcaster is selectively placed within said scan-based integrated circuit, inside said ATE, or between said ATE and said scan-based integrated circuit.

106. The method of claim 96, wherein said compactor is selectively an XOR network or a multiple-input signature register (MISR), wherein said multiple-input signature register (MISR) further comprises a plurality of XOR gates and a plurality of memory elements, such as D flip-flops or D latches.

107. The method of claim 96, wherein said compactor further comprises using a mask network to enable or disable testing or diagnosis of selected scan cells in selected scan chains, wherein said mask network includes one or more AND gates.

108. The method of claim 96, wherein said compactor is selectively placed within said scan-based integrated circuit, inside said ATE, or between said ATE and said scan-based integrated circuit.