Gain block with stable internal bias from low-voltage power supply

• US 20030155977A1
• Filed: 12/13/2002
• Published: 08/21/2003
• Est. Priority Date: 06/06/2001
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Anadigics Incorporated (Coherent Corp.)
• Inventors: Johnson, Douglas M., Liwinski, Henry Z.
• Granted Patent: US 6,842,075 B2
• Time in Patent Office: Days
• US Class Current: 330/290
• CPC Class Codes: G05F 3/265 using bipolar transistors only
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 3/343 with semiconductor devices only

Abstract

A transistor bias circuit is provided that is capable of operating from a power supply voltage that is slightly higher than twice the base-emitter voltage of the transistor to be biased. The bias circuit includes a transistor connected in a current-mirror configuration with the transistor to be biased. A feedback circuit maintains the mirrored current at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit. In a preferred embodiment, the biased transistor is concurrently in both a Darlington and the current mirror configuration. Moreover, a feedback transistor in the feedback circuit is also concurrently in the Darlington configuration, thus providing an efficient biasing arrangement for an amplifier block based on the Darlington arrangement.

Claims

1. A circuit for biasing a first transistor having a control terminal, current-sink terminal, and current-source terminal and capable of operating at least from a first regulated power supply and a second power supply, the circuit comprising:

a. a second transistor having a control terminal, current-sink terminal and current-source terminal, wherein the control terminal of the second transistor is connected to the control terminal of the first transistor in a current-mirror configuration, and wherein the current-source terminal of the second transistor is connected to a first terminal of the first regulated power supply;

b. at least one resistor connected between the current-sink terminal of the second transistor and a second terminal of the first regulated power supply;

c. a feedback circuit, including a non-inverting amplifier having a feedback transistor, and input and output ports, wherein the input port of the non-inverting amplifier is connected to the at least one resistor and the current-sink terminal of the second transistor; and

wherein furthermore a control terminal of a feedback transistor is connected to the output port of the non-inverting amplifier, and a current-source terminal of the feedback transistor connected to the second transistor and the first transistor, with the current-sink terminal of the feedback transistor connected to the second terminal of the second power supply,

whereby the non-inverting amplifier increases the gain of the feedback circuit so that the bias circuit is relatively insensitive to fluctuations in supply voltage or temperature.

2. The circuit according to claim 1, wherein one of the second transistor and the feedback transistor is a BJT, an HBT, DHBT, or a FET.

3. The circuit according to claim 1, further comprising a second resistor coupled between the current-source terminal of the feedback transistor and the first terminal of the first power supply.

4. The circuit according to claim 1, further comprising:

a. a third resistor coupled between the control terminal of the first transistor and the current-source terminal of the feedback transistor; and

b. a fourth resistor coupled between the control terminal of the second transistor and the current-source terminal of the feedback transistor.

5. The circuit according to claim 1, wherein the non-inverting amplifier comprises two cascaded transistors, each having a control terminal, current-sink terminal, and current-source terminal.

6. A method of biasing a first transistor having a control terminal, a current-sink terminal, and a current-source terminal and capable of operating from a power supply having positive and ground terminals via a bias circuit including a second transistor connected in a current-mirror configuration with the first transistor, the method comprising the steps of:

a. monitoring an electrical characteristic at the current-sink terminal of the second transistor;

b. amplifying the monitored characteristic; and

c. feeding back the amplified characteristic to control the second transistor.

7. The method of claim 6, wherein the electrical characteristic is one of current and voltage.

8. The method of claim 6, wherein the step of amplifying comprises the steps of inverting the characteristic and then re-inverting the characteristic, the that a non-inverted amplified characteristic is produced.

9. The method of claim 6, further comprising the step of level-shifting the monitored characteristic.

10. A circuit for biasing one or more transistors, the circuit comprising:

a regulated low voltage supply terminal providing a reference current to a first transistor in a current mirror configuration;

an amplifier providing feedback to counteract variations;

a Darlington arrangement comprising a second transistor concurrently in the current mirror configuration;

an input coupled to at least one transistor in the Darlington arrangement;

an output terminal; and

a power supply connected to the second transistor and providing a biasing current to the Darlington arrangement in accordance with a mirror current to the second transistor in the current mirror configuration.

11. The circuit of claim 10, wherein the Darlington configuration consists essentially of two transistors.

12. The circuit of claim 10, wherein the Darlington configuration comprises at least three transistors.

13. The circuit of claim 10, wherein at least one transistor in the Darlington configuration is biased by a current mirror configuration comprising the at least one transistor in the Darlington configuration.

14. The circuit of claim 12, wherein all of the transistors in the Darlington configuration are biased by a current mirror configuration comprising at least one transistor in the Darlington configuration.

15. The circuit of claim 13, wherein the amplifier provides a feedback to adjust biasing of the first and second transistor to counteract variations in a voltage at a current sink terminal of the first transistor.

16. The method of claim 15, wherein the feedback includes a reactance to reduce the gain at high frequencies.

17. A method of biasing an amplification stage having a Darlington configuration with a biasing network having reduced power consumption, the method comprising:

providing a reference current to a master transistor from a regulated supply; and

providing a biasing current from another supply to one of the transistors in the Darlington arrangement such that the one of the transistors is in a current mirror configuration with the master transistor.

18. A method for designing a circuit for biasing a Darlington arrangement, the method comprising:

providing a reference current through a master transistor;

providing a mirror current substantially related to the reference current by a scaling factor through a first transistor in the Darlington arrangement; and

providing a biasing current through a second transistor coupled to the first transistor in the Darlington arrangement.

19. The method of claim 18 further comprising providing a feedback arrangement for stabilizing the biasing of the first transistor in the Darlington arrangement such that the second transistor in the Darlington arrangement is also a part of the feedback arrangement.

20. A circuit for biasing a plurality of transistors, the circuit comprising:

a regulated low voltage supply terminal providing a reference current to a first transistor in a current mirror configuration;

an amplifier providing feedback to counteract variations;

a cascade arrangement of transistors comprising a second transistor concurrently in the current mirror configuration;

an input coupled to at least one transistor in the cascade arrangement of transistors; and

an output terminal connected to a power supply providing a biasing current to the cascade arrangement of transistors in accordance with a mirror current to the second transistor in the current mirror configuration.

21. The circuit of claim 20, wherein the cascade arrangement of transistors is a Darlington arrangement.