Multi-level signal clock recovery technique

• US 20030156655A1
• Filed: 02/12/2003
• Published: 08/21/2003
• Est. Priority Date: 02/15/2002
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Quellan, Inc. (Renesas Electronics Corporation)
• Inventors: Kim, Andrew Joo, Hietala, Vincent Mark
• Granted Patent: US 7,212,580 B2
• Time in Patent Office: Days
• US Class Current: 375/293
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03K 5/1534 Transition or edge detectors
• CPC Class Codes: H04L 25/4917 using multilevel codes
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Clock recovery of a multi-level (ML) signal can be performed in a two-step process. First, the transitions within the ML signal can be detected by a novel transition detector (TD). And second, the output of the TD circuit can comprise a pseudo-non-return-to-zero (pNRZ) signal that can drive a conventional OOK clock recovery (CR) IC. The TD circuit can convert the edges of the ML signal into the pseudo-NRZ (pNRZ) signal. The TD circuit can capture as many transitions as possible to allow the conventional NRZ clock recovery (CR) chip to optimally perform. The TD circuit can differentiate the ML signal in order to detect the ML signal'"'"'s transitions.

Claims

1. A system for determining a clock signal from a multi-level signal comprising:

a transition detector for differentiating a multi-level signal to form a differentiated signal that enables detection of edges of the multi-level signal and for generating a binary signal based on the differentiated signal; and

a clock recovery unit for receiving the binary signal and determining a clock signal, whereby increased data transitions are realized from the multilevel signal and time for determining the clock signal and jitter are reduced.

2. The system of Claim 1, wherein the transition detector splits the differentiated signal into a first differentiated signal and a second differentiated signal.

3. The system of claim 2, wherein the transition detector thresholds the first differentiated signal against a predetermined value for detecting magnitudes of the first differentiated signal above the predetermined value.

4. The system of claim 2, wherein the transition detector thresholds the second differentiated signal against a predetermined value for detecting magnitudes of the second differentiated signal below the predetermined value.

5. The system of claim 1, wherein the transition detector splits the differentiated signal into two differentiated signals, and thresholds the two differentiated signals to detect upward and downward transitions, converts each of the two return-to-zero thresholded signals into a non-return-to-zero signal, and combines the two non-return-to-zero signals together to convey both upward and downward transitions in a single signal.

6. The system of claim 1, wherein the transition detector comprises a differentiator circuit.

7. The system of claim 1, wherein the transition detector comprises a comparator and a toggle flip flop.

8. The system of claim 1, wherein the transition detector comprises a shunt capacitor connected to an output of a low impedance emitter or source of a transistor.

9. A system for receiving a multi-level signal and determining a clock signal from the multi-level signal comprising:

a variable threshold transition detector for differentiating a multilevel signal to form a signal that enables detection of edges of the multi-level signal, for sampling the signal at different points in time and applying an adaptive threshold to the differentiated signal to form a thresholded signal, and for generating a binary signal based on the thresholded signal;

a clock recovery unit for receiving the binary signal and determining a clock signal, whereby increased data transitions are realized from the multilevel signal and the period of time for determining the clock signal and jitter are reduced.

10. The system of claim 9, wherein the variable threshold transition detector determines if a magnitude of a derivative based on the multilevel signal is greater than a predetermined threshold value.

11. The system of claim 9, wherein the variable threshold transition detector determines if a magnitude of a derivative based on the multilevel signal is less than a predetermined threshold value.

12. The system of claim 9, wherein the variable threshold transition detector splits the multilevel signal into two signals, differentiates the two signals, thresholds the differentiated signals against two predetermined values, and combines the thresholded signals into one signal.

13. The system of claim 12, wherein the variable threshold transition detector combines the thresholded signals into one signal by using one of an exclusive-or (XOR) and logical-or (OR) operation between the two signals.

14. The system of claim 9, wherein the variable threshold transition detector delays and splits the multilevel signal into at least two delayed signals, and differentiates and splits one of the delayed signals.

15. The system of claim 9, wherein the variable threshold transition detector delays and splits the multilevel signal into three delayed signals, differentiates one of the three delayed signals, and combines the signals back into one signal for further processing by the clock recovery unit.

16. A method for identifying a clock signal from a multi-level signal comprising:

receiving a multi-level signal;

differentiating the multi-level signal to form a differentiated signal;

detecting edges of the multilevel signal by thresholding the differentiated signal;

generating a binary signal based on the differentiated signal; and

identifying a clock signal from the binary signal, whereby increased data transitions are realized from the multilevel signal and a period of time for determining the clock signal and jitter are reduced.

17. The method claim 16, further comprising splitting the differentiated multi-level signal into a first differentiated signal and a second differentiated signal.

18. The method of claim 17, wherein thresholding the differentiated signal comprises comparing the first differentiated signal to a predetermined value for detecting magnitudes of the first differentiated signal above the predetermined value.

19. The method of claim 17, wherein thresholding the differentiated signal comprises comparing the second differentiated signal against a predetermined value for detecting magnitudes of the second differentiated signal below the predetermined value.

20. The method of claim 16, further comprising splitting the differentiated signal into two differentiated signals, thresholding the two differentiated signals to form two return-to-zero thresholded signals, converting the two return-to-zero thresholded signals into two non-return-to-zero signals, and combining the two non-return-to-zero signals back together.