Method for forming a hard mask in a layer on a planar device

• US 20030157436A1
• Filed: 02/20/2003
• Published: 08/21/2003
• Est. Priority Date: 02/20/2002
• Status: Active Grant

• Current Assignee: ChangXin Memory Technologies, Inc.
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Manger, Dirk, Goldbach, Matthias
• Granted Patent: US 7,005,240 B2
• Time in Patent Office: Days
• US Class Current: 430/311
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

A hard mask is produced from spacer structures. The spacer structures are formed from a conformal deposition on elevated structures produced lithographically in a projection process. The conformal deposition is etched back laterally on the elevated structures resulting in the spacer structures. The elevated structures between the spacer structures are subsequently etched away, so that the spacer structures remain in an isolated fashion as sublithographic structures of a hard mask with a doubled structure density compared with that originally produced in lithographic projection. In a regularly disposed two-dimensional array of structures in the hard mask for forming trenches—for instance for trench capacitors—the method achieves a doubling of the structure density in the array. A further iteration step is formed by forming further spacer structures on the first and second spacer structures, thereby achieving an even higher increase in structure density in the hard mask. REL/rit

Claims

1. A method for forming a hard mask in a first layer on a planar device, which comprises the steps of:

depositing a second layer on the first layer;

using a lithographic projection process for forming at least one elevated first structure from the second layer disposed above the first layer;

conformally depositing a third layer on the elevated first structure and on the first layer;

etching back the third layer for forming a first spacer structure and a second spacer structure each disposed on a respective side area of the elevated first structure; and

etching the second layer selectively with respect to the first and third layers to remove the elevated first structure disposed between the first and second spacer structures, resulting in the hard mask being formed from the first and second spacer structures.

2. The method according to claim 1, further comprising the steps of:

depositing conformally a fifth layer on the first layer and on the first and second spacer structures; and

etching back the fifth layer for forming a third spacer structure and a fourth spacer structure on a respective side of the first spacer structure and also a fifth spacer structure and a sixth spacer structure on a respective side of the second spacer structure.

3. The method according to claim 2, further comprising the steps of:

removing the first spacer structure formed from the third layer between the third and fourth spacer structures using a selective etching step; and

removing the second spacer structure formed between the fifth and sixth spacer structures using a further selective etching step.

4. The method according to claim 1, further comprising the steps of:

forming the first layer from silicon nitride;

forming the second layer from silicon oxide; and

forming the third layer from polysilicon.

5. The method according to claim 2, further comprising the step of forming the third and fifth layers from a same material.

6. The method according claim 1, further comprising the steps of:

carrying out the lithographic projection process in a projection apparatus with a minimum resoluble structure width; and

producing at least one of the spacer structures transferred to the first layer with a given structure width, the given structure width being smaller than the minimum resoluble structure width of the projection apparatus.

7. The method according to claim 2, which comprises during the lithographic projection process, forming an elevated second structure from the second layer, the elevated first and second structures have a given width and a mutual spacing there-between, the mutual spacing not being less than the given width and not being more than three times the given width.

8. The method according to claim 7, which comprises:

carrying out the depositing of the third layer with a first thickness; and

carrying out the depositing of the fifth layer with a second thickness, the first and second thicknesses being implemented in a manner dependent on the given width and the mutual spacing.

9. The method according to claim 8, which comprises:

forming the first thickness to be essentially half a difference between the mutual spacing and the given width of the first and second structures; and

forming the second thickness to be essentially an eighth of a difference between three times the given width and the mutual spacing.

10. The method according to claim 2, which comprises:

during the lithographic projection process, forming elevated second, third and fourth structures from the second layer before performing the step of etching the second layer, the elevated first to fourth structures are not disposed contiguously on the first layer and the elevated first structure has, in a first direction, a given spacing with respect to the elevated second structure and, in a second direction substantially perpendicular to the first direction, having the given spacing with respect to the elevated third structure; and

performing the etching of the second layer step to the first to fourth structures in a same way to form a hole structure enclosed by the third to sixth spacer structures of the fifth layer in the hard mask.

11. The method according to claim 10, which comprises:

providing a silicon substrate, the first layer bearing on the silicon substrate and is formed of silicon nitride;

forming the second layer from polysilicon;

forming the third layer and the fifth layer from silicon oxide; and

using the hard mask transferred to the first layer in an etching step for forming trench capacitors in a memory cell array.

12. The method according to claim 1, which comprises using one of a semiconductor wafer, a mask, and a flat panel as the planar device.

13. The method according to claim 1, further comprising the step of etching the first layer selectively with respect to the third layer, so that the first and second spacer structures are transferred to the first layer for forming a further hard mask.

14. A method for forming a hard mask in a first layer on a planar device, which comprises the steps of:

depositing a fourth layer on the first layer;

using a lithographic projection process for forming a hole structure in the fourth layer;

conformally depositing a third layer;

etching back the third layer for forming a first spacer structure and a second spacer structure on a respective side area of the hole structure;

depositing and filling the hole structure with a second layer;

planarizing the second layer;

etching the fourth layer selectively with respect to the first, second and third layers for forming an elevated first structure enclosed by the first and second spacer structures on the side areas; and

etching the second layer selectively with respect to the first and third layers for removing the elevated first structure between the first and second spacer structures, resulting in the hard mask being formed from the spacer structures.

15. The method according to claim 14, further comprising the steps of:

depositing conformally a fifth layer on the first layer and the spacer structures; and

etching back the fifth layer for forming a third and a fourth spacer structure on a respective side of the first spacer structure and also a fifth and a sixth spacer structure on a respective side of the second spacer structure.

16. The method according to claim 15, further comprising the steps of:

removing the first spacer structure formed from the third layer and disposed between the third and fourth spacer structures using a selective etching step; and

removing the second spacer structure disposed between the fifth and sixth spacer structures using a further selective etching step.

17. The method according to claim 14, further comprising the steps of:

forming the first layer from silicon nitride;

forming the second layer from silicon oxide; and

forming the third layer from polysilicon.

18. The method according to claim 15, further comprising the step of forming the third and fifth layers from a same material.

19. The method according claim 14, further comprising the steps of:

carrying out the lithographic projection process in a projection apparatus with a minimum resoluble structure width; and

producing at least one of the spacer structures transferred to the first layer with a given structure width, the given structure width produced for the at least one spacer structure is smaller than the minimum resoluble structure width of the projection apparatus.

20. The method according to claim 15, which comprises during the lithographic projection process, forming an elevated second structure from the second layer, the elevated first and second structures have a given width and a mutual spacing there-between, the mutual spacing not being less than the given width and not being more than three times the given width.

21. The method according to claim 20, which comprises:

carrying out the depositing of the third layer with a first thickness; and

carrying out the depositing of the fifth layer with a second thickness, the first and second thicknesses being implemented in a manner dependent on the given width and the mutual spacing.

22. The method according to claim 21, which comprises:

forming the first thickness to be essentially half a difference between the mutual spacing and the given width of the first and second structures; and

forming the second thickness to be essentially an eighth of a difference between three times the given width and the mutual spacing.

23. The method according to claim 15, which comprises:

during the lithographic projection process, forming elevated second, third and fourth structures from the second layer before performing the step of etching the second layer, the elevated first to fourth structures are not disposed contiguously on the first layer and the elevated first structure has, in a first direction, a given spacing with respect to the elevated second structure and, in a second direction substantially perpendicular to the first direction, having the given spacing with respect to the elevated third structure; and

performing the etching of the second layer step to the first to fourth structures in a same way for forming a hole structure enclosed by the third to sixth spacer structures of the fifth layer in the hard mask.

24. The method according to claim 23, which comprises:

providing a silicon substrate, the first layer bearing on the silicon substrate and is formed of silicon nitride;

forming the second layer from polysilicon;

forming the third layer and the fifth layer from silicon oxide; and

using the hard mask transferred to the first layer in an etching step for forming trench capacitors in a memory cell array.

25. The method according to claim 24, which comprises forming the fifth layer from borophosphosilicate glass.

26. The method according to claim 14, which comprises using one of a semiconductor wafer, a mask, and a flat panel as the planar device.

27. The method according to claim 14, further comprising the step of etching the first layer selectively with respect to the third layer, so that the first and second spacer structures are transferred to the first layer for forming a further hard mask.