Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices

• US 20030157748A1
• Filed: 02/20/2002
• Published: 08/21/2003
• Est. Priority Date: 02/20/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kim, Sarah E., List, R. Scott, Kellar, Scot A.
• Granted Patent: US 6,762,076 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

Claims

1. A method of vertically stacking wafers, comprising:

selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers;

bonding the adjacent wafers, via respective metallic lines on opposing surfaces of the adjacent wafers, to establish electrical connections between active devices on vertically stacked wafers; and

forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect.

2. The method as claimed in claim 1, wherein each via is formed by:

selectively etching the top wafer to form a via;

depositing an oxide layer to insulate a sidewall of the via;

forming a barrier/seed layer in the via; and

depositing a conduction metal on the barrier/seed layer in the via for providing an electrical connection between active devices on the vertically stacked wafers and the external interconnect.

3. The method as claimed in claim 1, wherein the metallic lines are Copper (Cu) lines deposited to serve as electrical contacts between active devices on the vertically stacked wafers.

4. The method as claimed in claim 2, wherein the conduction metal deposited in the via is copper (Cu) or a Cu alloy.

5. The method as claimed in claim 2, wherein the barrier/seed layer contains a barrier layer deposited in the via, and a copper (Cu) seed layer deposited in the trench overlying the barrier layer.

6. The method as claimed in claim 5, wherein the barrier layer is comprised of a material selected from one of the group including tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W), and the Cu seed layer is comprised of a thin layer of copper (Cu) deposited on the barrier layer by chemical vapor deposition (CVD) process.

7. The method as claimed in claim 1, further comprising dummy vias arranged on opposing surfaces of the adjacent wafers to increase the surface area for wafer-to-wafer bonding and serve as auxiliary structures such as ground planes or heat conduits for the active devices on the vertically stacked wafers.

8. The method as claimed in claim 1, wherein the vias are formed tapered from the top to the bottom via trench to increase the surface area for wafer to-wafer bonding in the adjacent wafers.

9. The method as claimed in claim 1, wherein each via is formed by a dual damascene process comprised of:

selectively etching the top wafer to form an upper trench section of a via;

depositing an oxide layer to insulate a sidewall of the upper trench section of the via;

selectively etching the oxide layer in the upper trench section of the via to form a lower trench section of the via;

depositing a barrier/seed layer in the upper trench section and the lower trench section of the via; and

depositing a conduction metal on the barrier/seed layer for providing an electrical connection between active devices on the vertically stacked wafers and an external interconnect.

10. The method as claimed in claim 9, wherein the barrier/seed layer includes a barrier layer comprised of a material selected from one of the group including tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W), and deposited in the upper trench section overlying the oxide layer and the lower trench section of the via;

and a copper (Cu) seed layer comprised of a thin layer of copper (Cu) deposited on the barrier layer, and deposited overlying the barrier layer in both the upper trench section and the lower trench section of the via.

11. The method as claimed in claim 1, wherein the vias are formed during a Shallow Trench Isolation (STI) process in the top wafer before the adjacent wafers are bonded, via the respective metallic lines deposited on opposing surfaces of the adjacent wafers.

12. A method of forming vertically stacked wafers, comprising:

depositing a plurality of metallic lines on opposing surfaces of top and bottom wafers;

forming a conductive plug;

bonding the adjacent wafers, via respective metallic lines, to form vertically stacked wafers; and

forming at least one via on the top wafer to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect, by selectively etching through the top wafer until stopped by the conductive plug, depositing an oxide layer to insulate a sidewall of the via, depositing a barrier/seed layer on the bottom of the via, and filling the via with a conduction metal to serve as electrical connections between active devices on the vertically stacked wafers and the external interconnect.

13. The method as claimed in claim 12, wherein the metallic lines are Copper (Cu) lines deposited to serve as electrical contacts between active devices on the vertically stacked wafers.

14. The method as claimed in claim 12, wherein the conduction metal deposited in the via is copper (Cu) or a Cu alloy.

15. The method as claimed in claim 12, wherein the barrier/seed layer contains a barrier layer deposited in the via, and a copper (Cu) seed layer deposited in the via overlying the barrier layer.

16. The method as claimed in claim 15, wherein the barrier layer is comprised of a material selected from one of the group including tantalum, titanium, and tungsten, and the Cu seed layer is comprised of a few layers of copper (Cu) atoms deposited on the barrier layer by chemical vapor deposition (CVD) process.

17. The method as claimed in claim 12, further comprising dummy vias arranged on opposing surfaces of the adjacent wafers to increase the surface area for wafer-to-wafer bonding and serve as auxiliary structures such as ground planes or heat conduits for the active devices on the vertically stacked wafers.

18. The method as claimed in claim 12, wherein the via is formed tapered from the top to the bottom via trench to increase the surface area for wafer to-wafer bonding in the adjacent wafers.

19. A three-dimensional (3-D) vertically stacked wafer system, comprising:

a first wafer including an active region to support one or more integrated circuit (IC) devices;

a second wafer including an active region to support one or more integrated circuit (IC) devices;

metallic lines deposited on opposing surfaces of the first and second wafers at designated areas to establish metal bonding between the first and second wafers in a stack and provide electrical connections between active IC devices on the first and second wafers in the stack; and

one or more vias formed, via the active region of the first wafer, to serve as electrical connections between the active IC devices on the first and second wafers in the stack and an external interconnect.

20. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 19, wherein the metallic lines include Copper (Cu) lines deposited on opposing surfaces of the first and second wafers to serve as electrical contacts between active IC devices on the first and second wafers.

21. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 20, wherein each via is formed by:

selectively etching the first wafer to form a via;

depositing an oxide layer to insulate a sidewall of the via;

forming a barrier/seed layer in the via; and

depositing a conduction metal on the barrier/seed layer in the via for providing an electrical connection between active IC devices on the vertically stacked wafers and the external interconnect.

22. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 21, wherein the conduction metal deposited in the via is copper (Cu) or a Cu alloy, and the barrier/seed layer includes a barrier layer deposited in the via overlying the oxide layer and a copper (Cu) seed layer deposited in the via overlying the barrier layer.

23. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 22, wherein the barrier layer is comprised of a material selected from one of the group including tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W), and the Cu seed layer is comprised of a thin layer of copper (Cu) deposited on the barrier layer by chemical vapor deposition (CVD) process.

24. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 20, wherein each via is formed by a dual damascene process comprised of:

selectively etching the top wafer to form an upper trench section of the via;

depositing an oxide layer to insulate a sidewall of the upper trench section of the via;

etching the oxide layer in the upper trench section to form a lower trench section of the via;

depositing a barrier/seed layer in the upper trench section and the lower trench section of the via; and

depositing a conduction metal on the barrier/seed layer for providing an electrical connection between active devices on the vertically stacked wafers and the external interconnect.

25. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 24, wherein the barrier/seed layer includes a barrier layer comprised of a material selected from one of the group including tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W), and deposited in the upper trench section overlying the oxide layer and the lower trench section of the via;

and a copper (Cu) seed layer comprised of a thin layer of copper (Cu) deposited on the barrier layer, and deposited overlying the barrier layer in both the upper trench section and the lower trench section of the via.

26. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 20, wherein the vias are formed during a Shallow Trench Isolation (STI) process in the first wafer before the first and second wafers are bonded, via the respective metallic lines deposited on opposing surfaces of the first and second wafers.

27. A three-dimensional (3-D) vertically stacked wafer system, comprising:

a first stack of wafers in which adjacent wafers are bonded, via metallic lines deposited on opposing surfaces of the adjacent wafers at designated areas to establish metal bonding between the adjacent wafers and provide electrical connections between active IC devices on the adjacent wafers;

a first stack of wafers in which adjacent wafers are bonded, via metallic lines deposited on opposing surfaces of the adjacent wafers at designated areas to establish metal bonding between the adjacent wafers and provide electrical connections between active IC devices on the adjacent wafers; and

one or more vias formed on opposing surfaces of the first stack of wafers and the second stack of adjacent wafers to serve as electrical connections between the active IC devices on the first and second stacks of wafers and an external interconnect.

28. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 27, wherein the metalic lines include Copper (Cu) lines deposited on opposing surfaces of the adjacent wafers in the first and second stacks of wafers to serve as electrical contacts between active IC devices on the first and second stacks of wafers.

29. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 27, further comprising dummy vias arranged on opposing surfaces of the first and second stacks of adjacent wafers to increase the surface area for wafer-to-wafer bonding and serve as auxiliary structures such as ground planes or heat conduits for the active IC devices on vertically stacked wafers.

30. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 27, wherein the vias are formed tapered from the top to the bottom via trench to increase the surface area for wafer to-wafer bonding in the first and second stacks of adjacent wafers.

31. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 27, wherein each via is formed by a dual damascene process comprised of:

selectively etching the top wafer to form an upper trench section of a via;

depositing an oxide layer to insulate a sidewall of the upper trench section of the via;

etching the oxide layer in the upper trench section of the via to form a lower trench section of the via;

depositing a barrier/seed layer in the upper trench section and the lower trench section of the via; and

depositing a conduction metal on the barrier/seed layer for providing an electrical connection between active IC devices on the vertically stacked wafers and the external interconnect.

32. The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 31, wherein the barrier/seed layer includes a barrier layer comprised of a material selected from one of the group including tantalum (Ta), tantalum (TaN), titanium (Ti), and tungsten (W), and deposited in the upper trench section overlying the oxide layer and the lower trench section of the via;

and a copper (Cu) seed layer comprised of a thin layer of copper (Cu) deposited on the barrier layer, and deposited overlying the barrier layer in both the upper trench section and the lower trench section of the via.