Method for testing a universal serial bus host controller

• US 20030159102A1
• Filed: 02/19/2003
• Published: 08/21/2003
• Est. Priority Date: 02/21/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chen, Hung-Pin, Lai, Ching-Chung
• Granted Patent: US 7,168,029 B2
• Time in Patent Office: Days
• US Class Current: 714/781
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

A chip test method is suitable for testing a universal serial bus host controller. First, the host controller and the client device are individually set in a test mode. Next, the client device performs a client-side test preparation action. In addition, the host controller performs a host-side test preparation action. The host controller sequentially outputs a number of requests to the client device. The client device, in response to the requests, outputs simulated responses individually to the host controller, wherein the simulated responses are selected from correct responses corresponding to the requests, possible faulty responses, and error responses that are possibly to be received by the host controller during actual operation. Finally, the host controller performs a verification test to verify whether the host controller works properly under the various simulated situations.

Claims

1. A method for testing a host controller, in which a client device is coupled to said host controller via a bus so as to test said host controller, said method comprising the steps of:

setting said host controller and said client device individually in a test mode;

performing a client-side test preparation action at said client device;

performing a host-side test preparation action at said host controller;

sequentially outputting a plurality of requests from said host controller to said client device;

in response to said requests, producing a plurality of simulated responses from said client device to said host controller, wherein said simulated responses are selected from correct responses corresponding to said requests, possible faulty responses, and error responses, which are possibly to be received by said host controller during actual operation; and

performing a verification test at said host controller.

2. The method as recited in claim 1, wherein said client device is installed on another host controller.

3. The method as recited in claim 1, wherein said client device is coupled to a memory device for storing the corresponding simulated responses.

4. The method as recited in claim 3, wherein said client device comprises a data buffer, and said client-side test preparation action comprises the step of:

reading said corresponding simulated responses from said memory device, and temporarily storing said requests and said corresponding simulated responses into said data buffer.

5. The method as recited in claim 4, wherein said data buffer is a synchronous dynamic random access memory (SDRAM).

6. The method as recited in claim 1, wherein said host controller is coupled to a memory device for storing said requests.

7. The method as recited in claim 6, wherein said host controller further comprises a data buffer, and said host-side test preparation action further comprises the step of:

reading said requests from said memory device, and temporarily storing said requests and said corresponding simulated responses into said data buffer.

8. The method as recited in claim 7, wherein said data buffer is a synchronous dynamic random access memory (SDRAM).

9. The method as recited in claim 1, wherein said verification test comprises the step of:

checking whether said response received by said host controller is correct, and whether status data stored in a plurality of status registers of said host controller is correct.

10. The method as recited in claim 1, wherein said bus is a universal serial bus (USB).

11. The method as recited in claim 10, wherein said universal serial bus is compliant with USB 2.0.