Active pixel sensor with intra-pixel charge transfer

• US 20030160238A1
• Filed: 03/12/2003
• Published: 08/28/2003
• Est. Priority Date: 01/28/1994
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Fossum, Eric R., Kemeny, Sabrina E., Mendis, Sunetra
• Granted Patent: US 6,744,068 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H01L 27/14843 Interline transfer
• CPC Class Codes: H01L 27/1485 Frame transfer
• CPC Class Codes: H01L 27/14887 Blooming suppression
• CPC Class Codes: H01L 31/02162 for filtering or shielding light, e.g. multicolour filters for photodetectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H04N 23/10 for generating image signals from different wavelengths
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 : Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 : comprising storage means other than floating diffusion

Abstract

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Claims

1. An imaging device, comprising:

a plurality of pixel cells, each of said cells comprising;

a substrate;

a photoreceptor, coupled to said substrate, to control accumulating photo-generated charge; and

a readout circuit comprising at least a buffering transistor configured as a follower to receive charge from said photoreceptor, and a selecting transistor, operating to select said each cell for readout; and

wherein said transistors in said readout circuit are formed of an integrated circuit technology which is compatible with complimentary metal oxide semiconductor (CMOS) technology, said substrate being of a first conductivity type, said readout circuit comprising transistors of a first conductivity type, a well region of a second conductivity type in said substrate and plural semiconductor transistors of a second conductivity type formed in said well region.

2. An imaging device as in claim 1, further comprising a microlens layer formed on at least part of the substrate to refract light incident on an area of the substrate that includes circuitry including at least said readout circuit, to the photoreceptor.

3. A device as in claim 1, further comprising a correlated double sampling circuit, obtaining a sample at a first time, prior to scene integration, obtains a second sample at a second time after scene integration, and produces an output indicative of a difference therebetween.

4. A device as in claim 3, wherein said correlated double sampling circuit which is formed with transistors of complementary types.

5. An imaging device, comprising

a plurality of pixel cells, each pixel cell comprising a photoreceptor, configured to receive light from a single pixel of a scene being imaged, a follower transistor, receiving information from said photoreceptor indicative of said light, a select transistor, selecting said each pixel cell for readout, said select transistor being energized to allow said information from said photoreceptor indicative of said light to be output,

wherein said photoreceptor, said follower transistor, and said select transistor are each formed of formation processes which are compatible with CMOS technology;

and

an associated device, associate with processing said light from said photoreceptors, formed in said substrate adjacent said plurality of pixels cells, and connected to receive said information from said pixels cells, wherein said associated device is formed of a plurality of CMOS transistors.

6. An imaging device as in claim 5 wherein said associated device is an image processing device.

7. An imaging device as in claim 5, wherein said associated device is a correlated double sampling device.

8. A method of acquiring an image, comprising:

definining a plurality of pixel areas, each said pixel area covering a specific optical area of a charge accumulating substrate;

configuring each of said plurality of pixel areas as a portion fo said substrate, providing a photogate controlling a characteristic of said charge accumulating substrate;

providing a sensing node which senses charge in said sensing charge accumulating substrate; and

associating a readout circuit with each of said sensing nodes of each of said pixel areas, in a way that each said pixel area includes a dedicated readout circuit.

9. A method as in claim 8, wherein a circuitry portion of said pixel area includes circuitry therein, and further comprising a lens system, covering at least said circuitry portion, and refracting impinging radiation to an area of said photogate.