Power semiconductor component, IGBT, IEGT, field-effect transistor, and method for fabricating the semiconductor component

• US 20030160270A1
• Filed: 01/28/2003
• Published: 08/28/2003
• Est. Priority Date: 01/28/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schaffer, Carsten, Pfirsch, Frank
• Granted Patent: US 6,815,769 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A trench power semiconductor component, in particular an IGBT, has an electrode (4) in a trench (3) that is laterally divided into a section (10) that serves as a gate and a section (11) that is connected to the source metallization (6). A method for making the trench power semiconductor component is also included.

Claims

1. A power semiconductor component, comprising:

a semiconductor body having a surface with a trench formed therein, said trench having a lower region;

an electrode device provided in said trench and having two electrodes electrically isolated from one another;

a first semiconductor zone of a first conductivity type, adjoining said trench, and having a metallization provided on said surface of said semiconductor body;

a second semiconductor zone of said first conductivity type and adjoining said lower region of said trench; and

a third semiconductor zone of a second conductivity type opposite to said first conductivity type, adjoining said trench, and separating said first semiconductor zone from said second semiconductor zone.

2. The power semiconductor component according to claim 1, further comprising a gate electrode connected to a first of said electrodes;

a second of said electrodes being connected to said metallization.

3. The power semiconductor component according to claim 2, wherein said first of said electrodes extends at least as deep as said second semiconductor zone.

4. The power semiconductor component according to claim 3, wherein:

said trench has a bottom; and

said first of said electrodes extends as far as said bottom of said trench.

5. The power semiconductor component according to claim 1, wherein said first semiconductor zone adjoins said surface.

6. The power semiconductor component according to claim 1, wherein said semiconductor body has a further surface opposing said surface of said semiconductor body;

a further metallization provided on said further surface.

7. The power semiconductor component according to claim 1, wherein said two electrodes of said electrode device are mutually adjacent.

8. The power semiconductor component according to claim 1, wherein:

said semiconductor body has an intercell region; and

a first of said electrodes of said electrode device is connected to said metallization and includes a section overlapping said intercell region.

9. The power semiconductor component according to claim 8, wherein said first of said electrodes is connected to said metallization in said intercell region.

10. The power semiconductor component according to claim 1, further comprising a gate connection being connected to a first of said electrodes of said electrode device;

a second of said electrodes being connected to said metallization;

said first of said electrodes including a section at least partially overlapping said second of said electrodes.

11. The power semiconductor component according to claim 1, wherein:

said semiconductor body has an intercell region; and

said electrode device is at least partly configured in step form over said intercell region.

12. The power semiconductor component according to claim 1, wherein said trench and said electrode device have a strip structure.

13. The power semiconductor component according to claim 12, wherein:

said strip structure has a strip end; and

a gate connection is disposed at said strip end.

14. The power semiconductor component according to claim 1, wherein said trench and said electrode device laterally surround said third semiconductor zone.

15. The power semiconductor component according to claim 14, wherein said third semiconductor zone has a polygon shape when seen from above.

16. The power semiconductor component according to claim 15, wherein said polygon shape is selected from the group consisting of a square and a hexagon.

17. The power semiconductor component according to claim 1, wherein said semiconductor body has an intercell region with a floating region.

18. The power semiconductor component according to claim 17, wherein said floating region has said second conductivity type.

19. The power semiconductor component according to claim 1, wherein said semiconductor body has an intercell region and a further trench in said intercell region.

20. The power semiconductor component according to claim 1, further comprising a connection separate from a gate connection and said metallization and connected to one of said electrodes of said electrode device.

21. The power semiconductor component according to claim 1, further comprising an insulation layer isolating said electrodes of said electrode device and being selected from the group consisting of silicon dioxide, silicon nitride, and a plurality of films with at least one of said films being made from silicon dioxide and at least one of said films being silicon nitride.

22. The power semiconductor component according to claim 1, wherein:

said semiconductor body has an intercell region;

a first of said electrodes has a width; and

said trench forms a wide trench spanning said intercell region and having a width greater than said width of said first of said electrodes.

23. The power semiconductor component according to claim 6, wherein at least one of said metallizations is made of aluminum.

24. The power semiconductor component according to claim 1, wherein said metallization is made of aluminum.

25. The power semiconductor component according to claim 1, wherein said electrode device is made of polycrystalline silicon.

26. An IGBT, comprising:

a semiconductor body having a surface with a trench formed therein, said trench having a lower region;

an electrode device provided in said trench and having two electrodes electrically isolated from one another;

a first semiconductor zone of a first conductivity type, adjoining said trench, and having a metallization provided on said-surface of said semiconductor body;

a second semiconductor zone of said first conductivity type and adjoining said lower region of said trench; and

a third semiconductor zone of a second conductivity type opposite to said first conductivity type, adjoining said trench, and separating said first semiconductor zone from said second semiconductor zone.

27. An IEGT, comprising:

a semiconductor body having a surface with a trench formed therein, said trench having a lower region;

an electrode device provided in said trench and having two electrodes electrically isolated from one another;

a first semiconductor zone of a first conductivity type, adjoining said trench, and having a metallization provided on said surface of said semiconductor body;

a second semiconductor zone of said first conductivity type and adjoining said lower region of said trench; and

a third semiconductor zone of a second conductivity type opposite to said first conductivity type, adjoining said trench, and separating said first semiconductor zone from said second semiconductor zone.

28. A field-effect transistor, comprising:

a semiconductor body having a surface with a trench formed therein, said trench having a lower region;

an electrode device provided in said trench and having two electrodes electrically isolated from one another;

a first semiconductor zone of a first conductivity type, adjoining said trench, and having a metallization provided on said surface of said semiconductor body;

a second semiconductor zone of said first conductivity type and adjoining said lower region of said trench; and

a third semiconductor zone of a second conductivity type opposite to said first conductivity type, adjoining said trench, and separating said first semiconductor zone from said second semiconductor zone.

29. A method for fabricating a power semiconductor component, which comprises:

(a) etching a trench having a lower part into a semiconductor body, the semiconductor body having a surface;

(b) producing a gate insulation layer on the surface of the semiconductor body and on the trench;

(c) producing a polycrystalline silicon layer on the gate insulation layer;

(d) depositing a first layer of material to mask the polycrystalline silicon layer;

(e) introducing a second layer of material for masking a subsequent etch of the first layer of material, at least in the lower part of the trench, the second layer of material not masking a region of the first layer of material;

(f) removing the first layer of material in the region not masked by the second layer of material;

(g) removing the second layer of material;

(h) producing a first insulating layer on the polycrystalline silicon layer in the region not masked by the first layer of material;

(i) anisotropically etching the polycrystalline silicon layer in the region at the base of the trench not masked by the first insulation layer,

(j) patterning the polycrystalline silicon layer;

(k) applying a second insulation layer;

(l) etching contact holes through the second insulation layer to the semiconductor body; and

(m) applying a metallization.

30. The method according to claim 29, which further comprises using a silicon dioxide layer as the gate insulation layer.

31. The method according to claim 29, which further comprises using a silicon nitride layer as the first layer of material.

32. The method according to claim 29, which further comprises using a photoresist layer as the second layer of material.

33. The method according to claim 29, which further comprises using a silicon dioxide layer as the first insulation layer.

34. The method according to claim 33, which further comprises producing the first insulation layer by thermal oxidation.

35. The method according to claim 29, which further comprises using a silicon dioxide layer as the second insulation layer.

36. The method according to claim 29, which further comprises etching trenches into the semiconductor body and the polycrystalline silicon layer during the etching of the contact holes.

37. The method according to claim 29, which further comprises carrying out the following steps between steps (i) and (j):

(i1) applying a thin insulating layer in the trench, the thin insulating layer not completely filling the trench; and

(i2) filling the trench with a further poly-crystalline silicon layer.

38. The method according to claim 29, which further comprises performing the following additional steps between steps (i) and (j):

(i1) applying a thin insulating layer in the trench, the thin insulating layer not completely filling the trench; and

(i3) at least partially removing the insulation layer on a cell side that is adjacent to the third semiconductors zone; and

(i4) applying a further polycrystalline silicon layer to a surface of the polycrystalline silicon layer and of the insulation layer and also into the trench.

39. The method according to claim 37, which further comprises selecting the insulation layer from the group consisting of a silicon dioxide layer and a silicon nitride layer.

40. The method according to claim 38, which further comprises selecting the insulation layer from the group consisting of a silicon dioxide layer and a silicon nitride layer.

41. The method according to claim 29, which further comprises, in step (j), jointly patterning the polycrystalline silicon layer and the further polycrystalline silicon layer in the regions that are not isolated by the insulation layer.

42. The method according to claim 29, which further comprises producing a further insulation layer on the polycrystalline silicon layer between steps (c) and (d).

43. The method according to claim 42, which further comprises using a silicon dioxide layer as the further insulation layer.

44. The method according to claim 29, wherein, in step (m), the metallization is applied to the semiconductor body.