Scalable gate and storage dielectric

• US 20030160277A1
• Filed: 02/27/2003
• Published: 08/28/2003
• Est. Priority Date: 11/09/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Granted Patent: US 6,998,667 B2
• Time in Patent Office: Days
• US Class Current: 257/310
• CPC Class Codes: H01L 21/02049 with gaseous HF
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3143 composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
• CPC Class Codes: H01L 21/3162 on a silicon body
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66181 : Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 12/033 : the capacitor extending over the transistor
• CPC Class Codes: H10B 12/038 : the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/312 : with a bit line higher than the capacitor

Abstract

Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.

Claims

1. A gate dielectric stack used in integrated circuit devices, said stack comprising:

a substrate;

a high K gate dielectric having a first and a second surface, said second surface forming an interface with said substrate, said interface having a charge no greater than about 3e+10 fundamental charge units per cm²;

a gate; and

a passivated overlayer having a first and a second surface, said second surface of said passivated overlayer forming a first chemically inert interface with said first surface of said high K gate dielectric, said first surface of said passivated overlayer forming a second chemically inert interface with said gate;

wherein

said K is a dielectric constant.

2. The gate dielectric stack of claim 1 wherein said substrate comprises silicon.

3. The gate dielectric stack of claim 1 wherein said high K gate dielectric has a K greater than about 10.

4. The gate dielectric stack of claim 1 wherein said high K gate dielectric comprises alumina.

5. The gate dielectric stack of claim 4 wherein said high K gate dielectric has a K in the range of about 11 to about 12.

6. The gate dielectric stack of claim 1 wherein said high K gate dielectric has a K greater than about 15.

7. The gate dielectric stack of claim 1 wherein said high K gate dielectric comprises alumina doped with a dopant.

8. The gate dielectric stack of claim 7 wherein said dopant is selected from the group consisting of silicon and a transition metal.

9. The gate dielectric stack of claim 8 wherein said transition metal is selected from the group consisting of zirconium, tungsten, hafnium, titanium, and tantalum.

10. The gate dielectric stack of claim 1 wherein said gate comprises material selected from the group consisting of degenerate heavily doped polysilicon and metal.

11. The gate dielectric stack of claim 1 wherein said passivated overlayer comprises silicon-rich-nitride.

13. The gate dielectric stack of claim 11 wherein said passivated overlayer has a thickness in the range of about 0.5 to about 3 nm.

14. A storage dielectric stack used in integrated circuit devices, said stack comprising:

a first plate;

a high K storage dielectric having a first and a second surface, said second surface forming an interface with said first plate, said interface having a charge no greater than about 3e+10 fundamental charge units per cm²;

a second plate; and

a passivated overlayer having a first and a second surface, said second surface of said passivated overlayer forming a first chemically inert interface with said first surface of said high K storage dielectric, said first surface of said passivated overlayer forming a second chemically inert interface with said second plate;

wherein

said K is a dielectric constant.

15. The storage dielectric stack of claim 14 wherein said first plate comprises degenerate heavily doped silicon.

16. The storage dielectric stack of claim 14 wherein said high K storage dielectric has a K greater than about 10.

17. The storage dielectric stack of claim 14 wherein said high K storage dielectric comprises alumina.

18. The storage dielectric stack of claim 17 wherein said high K storage dielectric has a K in the range of about 11 to about 12.

19. The storage dielectric stack of claim 14 wherein said high K storage dielectric has a K greater than about 15.

20. The storage dielectric stack of claim 14 wherein said high K storage dielectric comprises alumina doped with a dopant.

21. The storage dielectric stack of claim 20 wherein said dopant is selected from the group consisting of silicon and a transition metal.

22. The storage dielectric stack of claim 21 wherein said transition metal is selected from the group consisting of zirconium, tungsten, hafnium, titanium, and tantalum.

23. The storage dielectric stack of claim 14 wherein said second plate comprises material selected from the group consisting of doped polysilicon and metal.

24. The storage dielectric stack of claim 14 wherein said passivated overlayer comprises silicon-rich-nitride.

25. The storage dielectric stack of claim 24 wherein said silicon-rich-nitride has a refractive index of greater than about 2.5.

26. The storage dielectric stack of claim 24 wherein said passivated overlayer has a thickness in the range of about 0.5 to about 3 nm.

27. A gate dielectric stack used in integrated circuit devices, said stack comprising:

a substrate;

an alumina gate dielectric having a first and a second surface, said second surface forming an interface with the substrate;

a gate; and

a silicon-rich-nitride overlayer having a first and a second surface, said second surface of said silicon-rich-nitride overlayer forming a first chemically inert interface with said first surface of said alumina gate dielectric, said first surface of said silicon-rich-nitride overlayer forming a second chemically inert interface with said gate.

28. The gate dielectric stack of claim 27 wherein said substrate comprises silicon.

29. The gate dielectric stack of claim 27 wherein said alumina gate dielectric has a K in the range of about 11 to about 12 and said K is a dielectric constant.

30. The gate dielectric stack of claim 27 wherein said alumina gate dielectric is doped with a dopant.

31. The gate dielectric stack of claim-30 wherein said dopant is selected from the group consisting of silicon and a transition metal.

32. The gate dielectric stack of claim 27 wherein said silicon-rich-nitride overlayer has a refractive index of greater than about 2.5.

33. The gate dielectric stack of claim 27 wherein said silicon-rich-nitride overlayer has a thickness in the range of about 0.5 to about 3 nm.

34. The gate dielectric stack of claim 27 wherein said interface has a charge no greater than about 3e+10 fundamental charge units per cm².

35. A storage dielectric stack used in integrated circuit devices, said stack comprising:

a first plate;

an alumina storage dielectric having a first and a second surface, said second surface forming an interface with said first plate;

a second plate; and

a silicon-rich-nitride overlayer having a first and a second surface, said second surface of said silicon-rich-nitride overlayer forming a first chemically inert interface with said first surface of said alumina storage dielectric, said first surface of said silicon-rich-nitride overlayer forming a second chemically inert interface with said second plate.

12. The gate dielectric stack of claim 41 wherein said silicon-rich-nitride has a refractive index of greater than about 2.5.

36. The storage dielectric stack of claim 35 wherein said first plate comprises degenerate heavily doped silicon.

37. The storage dielectric stack of claim 35 wherein said alumina storage dielectric has a K in the range of about 11 to about 12 and said K is a dielectric constant.

38. The storage dielectric stack of claim 35 wherein said alumina storage dielectric is doped with a dopant.

39. The storage dielectric stack of claim-38 wherein said dopant is selected from the group consisting of silicon and a transition metal.

40. The storage dielectric stack of claim 35 wherein said silicon-rich-nitride overlayer layer has a refractive index of greater than about 2.5.

41. The storage dielectric stack of claim 35 wherein said silicon-rich-nitride overlayer has a thickness in the range of about 0.5 to about 3 nm.

42. The storage dielectric stack of claim 35 wherein said interface has a charge no greater than about 3e+10 fundamental charge units per cm².

43. A gate dielectric stack used in integrated circuit devices, said stack comprising:

a substrate;

an alumina gate dielectric having a first and a second surface, said second surface forming an interface with said substrate, said alumina gate dielectric having a K in the range of about 11 to about 12, said K being a dielectric constant, said interface having a charge no greater than about 3e+10 fundamental charge units per cm²;

a gate; and

a silicon-rich-nitride overlayer having a first and a second surface, said second surface of said silicon-rich-nitride overlayer forming a first chemically inert interface with said first surface of said alumina gate dielectric, said first surface of said silicon-rich-nitride overlayer forming a second chemically inert interface with said gate, said silicon-rich-nitride overlayer having a refractive index greater than or equal to about 2.5, said silicon-rich-nitride layer having a thickness in the range of about 0.5 to about 3 nm.

44. The gate dielectric stack of claim 43 wherein said alumina gate dielectric is doped with a dopant.

45. The gate dielectric stack of claim 44 wherein said dopant is selected from the group consisting of silicon and a transition metal.

46. A storage dielectric stack used in integrated circuits, said stack comprising:

a first plate;

an alumina storage dielectric having a first and a second surface, said second surface forming an interface with said first plate, said interface having a charge no greater than about 3e+10 fundamental charge units per cm²;

a second plate; and

a silicon-rich-nitride overlayer having a first and a second surface, said second surface of said silicon-rich-nitride overlayer forming a first chemically inert interface with said first surface of said alumina storage dielectric, said first surface of said silicon-rich-nitride overlayer forming a second chemically inert interface with said second plate, said silicon-rich-nitride overlayer having a refractive index greater than or equal to about 2.5, said silicon-rich-nitride layer having a thickness in the range of about 0.5 to about 3 nm.

47. The storage dielectric stack of claim 46 wherein said alumina storage dielectric is doped with a dopant.

48. The storage dielectric stack of claim 47 wherein said dopant is selected from the group consisting of silicon and a transition metal.

49. A method of fabricating a gate dielectric stack for a field effect transistor, said method comprising:

removing native Si_xO_yH_z from a region of a substrate;

depositing on said region a layer of metal that forms a high K dielectric material when oxidized;

oxidizing said layer to form said high K dielectric material;

depositing a passivated overlayer on said layer;

depositing a gate on said passivated overlayer; and

depositing a gate electrode on said gate;

wherein

said K is a dielectric constant.

50. The method of claim 49 further comprising doping said high K dielectric material.

51. The method of claim 50 wherein said doping comprises doping said high K dielectric material with a material selected from the group consisting of silicon and a transition metal.

52. The method of claim 51 wherein said transition metal is selected from the group consisting of zirconium, tungsten, hafnium, titanium, and tantalum.

53. The method of claim 49 further comprising annealing said gate dielectric stack by rapid thermal annealing to stabilize said stack.

54. The method of claim 53 wherein said annealing said gate dielectric stack is performed immediately following said depositing a passivated overlayer.

55. The method of claim 53 wherein said annealing said gate dielectric stack is performed immediately following said oxidizing.

56. The method of claim 49 wherein said removing native Si_xO_yH_z comprises:

inserting said substrate into a vacuum chamber;

controllably introducing hydrofluoric acid vapor in an ultra pure nitrogen bleed-in; and

maintaining a vacuum in said vacuum chamber of less than about 10<sup>−

6</sup> torr during said introducing.

57. The method of claim 49 wherein said depositing a layer of metal comprises depositing a layer of metal by a process selected from the group consisting of atomic layer deposition, molecular beam epitaxy, electron beam evaporation, and sputtering.

58. The method of claim 49 wherein said depositing a layer of metal comprises depositing a layer of aluminum.

59. The method of claim 49 wherein said depositing a layer of metal comprises depositing a layer of aluminum having a thickness of less than about 3 nm.

60. The method of claim 49 wherein said depositing a passivated overlayer comprises depositing a passivated overlayer of silicon-rich-nitride by a low pressure plasma enhanced chemical vapor deposition with SiH₄ or SiH₂Cl₂, NH₃, and nitrogen such that the ratio of SiH₄ or SiH₂Cl₂ to NH₃ is no less than about 15.

61. The method of claim 49 wherein said depositing a passivated overlayer comprises depositing an overlayer of silicon-rich-nitride having a refractive index greater than about 2.5.

62. The method of claim 49 wherein said depositing a passivated overlayer comprises depositing an overlayer of silicon-rich-nitride having a thickness in the range of about 0.5 to about 3 nm.

63. A method of fabricating a storage dielectric stack for an integrated circuit device, said method comprising:

removing native Si_xO_yH_z from a region of a first plate;

depositing on said region a layer of metal that forms a high K dielectric material when oxidized;

oxidizing said layer to form said high K dielectric material;

depositing a passivated overlayer on said layer; and

depositing a second plate on said passivated overlayer;

wherein

said K is a dielectric constant.

64. The method of claim 63 further comprising doping said high K dielectric material.

65. The method of claim 64 wherein said doping comprises doping said high K dielectric material with a material selected from the group consisting of silicon and transition metal.

66. The method of claim 65 wherein said transition metal is selected from the group consisting of zirconium, tungsten, hafnium, titanium, and tantalum.

67. The method of claim 63 further comprising annealing said storage dielectric stack by rapid thermal annealing to stabilize said stack.

68. The method of claim 67 wherein said annealing said gate dielectric stack is performed immediately following said depositing a passivated overlayer.

69. The method of claim 67 wherein said annealing said gate dielectric stack is performed immediately following said oxidizing.

70. The method of claim 63 wherein said removing native Si_xO_yH_z comprises:

inserting said first plate into a vacuum chamber;

controllably introducing hydrofluoric acid vapor in an ultra pure nitrogen bleed-in; and

maintaining a vacuum in said vacuum chamber of less than about 10<sup>−

6</sup> torr during said introducing.

71. The method of claim 63 wherein said depositing a layer of metal comprises depositing a layer of metal by a process selected from the group consisting of atomic layer deposition, molecular beam epitaxy, electron beam evaporation, and sputtering.

72. The method of claim 63 wherein said depositing a layer of metal comprises depositing a layer of aluminum.

73. The method of claim 63 wherein said depositing a layer of metal comprises depositing a layer of aluminum having a thickness of less than about 3 nm.

74. The method of claim 63 wherein said depositing a passivated overlayer comprises depositing a passivated overlayer of silicon-rich-nitride by a low pressure plasma enhanced chemical vapor deposition with SiH₄ or SiH₂Cl₂, NH₃, and nitrogen such that the ratio of SiH₄ or SiH₂Cl₂ to NH₃ is no less than about 15.

75. The method of claim 63 wherein said depositing a passivated overlayer comprises depositing an overlayer of silicon-rich-nitride having a refractive index not less than about 2.5.

76. The method of claim 63 wherein said depositing a passivated overlayer comprises depositing an overlayer of silicon-rich-nitride having a thickness in the range of about 0.5 to about 3 nm.

77. A method of fabricating a gate dielectric stack for a field effect transistor, said method comprising:

removing native Si_xO_yH_z from a region of a substrate;

depositing a layer of aluminum having a thickness of less than about 3 nm on said region;

oxidizing said layer of aluminum to form a layer of alumina;

depositing a passivated overlayer of silicon-rich-nitride on said layer of alumina by a low pressure plasma enhanced chemical vapor deposition process, said passivated overlayer having a thickness of about 0.5 to about 3 nm, said passivated overlayer is having a refractive index no less than about 2.5, said low pressure chemical vapor deposition process using SiH₄ or SiH₂Cl₂, NH₃, and nitrogen such that the ratio of SiH₄ or SiH₂Cl₂ to NH₃ is no less than about 15;

depositing a gate on said passivated overlayer; and

depositing a gate electrode on said gate.

78. The method of claim 77 further comprising annealing said gate dielectric stack by rapid thermal annealing to stabilize said stack.

79. The method of claim 78 wherein said annealing said gate dielectric stack is performed immediately following said depositing a passivated overlayer.

80. The method of claim 78 wherein said annealing said gate dielectric stack is performed immediately following said oxidizing.

81. The method of claim 77 wherein said removing native Si_xO_yH_z comprises:

inserting said substrate into a vacuum chamber;

controllably introducing hydrofluoric acid vapor in an ultra pure nitrogen bleed-in; and

maintaining a vacuum in said vacuum chamber of less than about 10<sup>−

6</sup> torr during said introducing.

82. A method of fabricating a storage dielectric stack for an integrated circuit device, said method comprising:

removing native Si_xO_yH_z from a region of a first plate;

depositing a layer of aluminum having a thickness of less than about 3 nm on said region;

oxidizing said layer of aluminum to form a layer of alumina;

depositing a passivated overlayer of silicon-rich-nitride on said layer of alumina by a low pressure plasma enhanced chemical vapor deposition process, said passivated overlayer having a thickness of about 0.5 to about 3 nm, said passivated overlayer is having a refractive index no less than about 2.5, said low pressure chemical vapor deposition process using SiH₄ or SiH₂Cl₂, NH₃, and nitrogen such that the ratio of SiH₄ or SiH₂Cl₂ to NH₃ is no less than about 15; and

depositing a second plate on said passivated overlayer.

83. The method of claim 82 further comprising annealing said storage dielectric stack by rapid thermal annealing to stabilize the stack.

84. The method of claim 83 wherein said annealing said gate dielectric stack is performed immediately following said depositing a passivated overlayer.

85. The method of claim 83 wherein said annealing said gate dielectric stack is performed immediately following said oxidizing.

86. The method of claim 82 wherein said removing native Si_xO_yH_z comprises:

inserting said first plate into a vacuum chamber;

controllably introducing hydrofluoric acid vapor in an ultra pure nitrogen bleed-in; and

maintaining a vacuum in said vacuum chamber of less than about 10<sup>−

6</sup> torr during said introducing.