Micro-machined semiconductor package

• US 20030160310A1
• Filed: 02/26/2002
• Published: 08/28/2003
• Est. Priority Date: 02/26/2002
• Status: Active Grant

• Current Assignee: CTS Corporation
• Original Assignee: CTS Corporation
• Inventors: Langhorn, Jason Barnabas
• Granted Patent: US 6,965,168 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

A hermetic multi-layered ceramic semiconductor package for micro-machined semiconductor devices. The package has a substrate with top and bottom surfaces. A micro-machined semiconductor device is located adjacent to the top surface. Vias extend through the substrate between the surfaces. The micro-machined semiconductor device is electrically connected to the vias. A rigid support is located between the micro-machined semiconductor device and the top surface to support the micro-machined semiconductor device during assembly and to space the micro-machined semiconductor device from the top surface. Solder spheres are mounted to the bottom surface and are connected to the vias.

Claims

1. A semiconductor package for a micro-machined semiconductor device, comprising:

a) a substrate having a first surface and a second surface, the micro-machined semiconductor device located adjacent the first surface;

b) a plurality of vias, extending through the substrate between the first and second surfaces;

c) an electrical connection located between the vias and the micro-machined semiconductor device for electrically connecting the vias to the semiconductor device;

d) a seal, located between the micro-machined semiconductor device and the first surface for hermetically sealing the micro-machined semiconductor device;

e) a rigid support located between the micro-machined semiconductor device and the first surface for supporting the micro-machined semiconductor device during assembly; and

f) a plurality of solder spheres mounted to the second surface and electrically connected to the vias.

2. The semiconductor package according to claim 1, wherein the electrical connection includes:

a) a first pad located on the micro-machined semiconductor device; and

b) a second pad located on the first surface; and

c) a solder joint connected between the first and second pad.

3. The semiconductor package according to claim 1, wherein the substrate is a low temperature co-fired ceramic.

4. The semiconductor package according to claim 1, wherein the seal is a ring of solder located adjacent an outer perimeter of the substrate.

5. The semiconductor package according to claim 1, wherein the rigid support is attached to the first surface.

6. The semiconductor package according to claim 5, wherein the rigid support is gold.

7. The semiconductor package according to claim 5, wherein the rigid support is an alloy of gold and palladium.

8. The semiconductor package according to claim 5, wherein the rigid support is ultrasonically deposited.

9. The semiconductor package according to claim 3, wherein the substrate has a plurality of layers.

11. The semiconductor package according to claim 1, wherein a ball pad is attached to the second surface, the solder sphere attached to the ball pad.

12. The semiconductor package according to claim 11, wherein the solder sphere is attached to the ball pad by a reflowed solder paste.

10. The semiconductor package according to claim 10, wherein a plurality of circuit lines are located on the layers, the circuit lines connected between the vias.

13. A semiconductor package for a micro-machined semiconductor device comprising:

a) a low temperature co-fired ceramic substrate having a plurality of layers, the substrate having a top and a bottom surface;

b) a plurality of vias, extending between the layers;

c) a plurality of solder spheres, located on the bottom surface and electrically connected to the vias;

d) a plurality of rigid supports, attached to the top surface;

e) a seal located between the micro-machined semiconductor device and the top surface, the seal hermetically sealing the micro-machined semiconductor device;

f) the micro-machined semiconductor device spaced from the top surface by the rigid supports such that a movable portion of the micro-machined semiconductor device is unconstrained for movement; and

g) an electrical connection located between the vias and the micro-machined semiconductor device for electrically connecting the vias to the semiconductor device.

14. The semiconductor package according to claim 13, wherein the electrical connection includes:

a) a first pad located on the micro-machined semiconductor device; and

b) a second pad located on the top surface; and

c) a solder joint connected between the first and second pad.

15. The semiconductor package according to claim 13, wherein the seal is a ring of solder located adjacent an outer perimeter of the substrate.

16. The semiconductor package according to claim 13, wherein the rigid support is gold.

17. The semiconductor package according to claim 13, wherein the rigid support is an alloy of gold and palladium.

18. The semiconductor package according to claim 13, wherein the rigid support is ultrasonically deposited.

19. The semiconductor package according to claim 13, wherein a plurality of circuit lines are located on the layers, the circuit lines connected between the vias.

20. The semiconductor package according to claim 13, wherein a ball pad is attached to the bottom surface, the solder sphere attached to the ball pad.

21. The semiconductor package according to claim 13, wherein the solder sphere is attached to the ball pad by a reflowed solder paste.

22. A method of making a semiconductor package comprising the steps of:

a) punching vias in at least two low temperature co-fired ceramic layers;

b) filling the vias with a conductor;

c) screen printing conductor lines on the layers;

d) screen printing a seal ring and a plurality of pads on one of the layers;

e) screen printing a plurality of ball pads on one of the layers;

f) stacking the layers;

g) laminating under pressure the layers into a substrate;

h) firing the substrate in an oven;

i) depositing a rigid support on the substrate;

j) screening a first solder paste onto the seal ring and the pads;

k) placing a micro-machined semiconductor device onto the substrate;

I) reflowing the first solder paste in an oven such that the micro-machined semiconductor device is attached to the substrate;

m) screening a second solder paste onto the ball pads;

n) placing a plurality of solder spheres onto the ball pads; and

o) reflowing the second solder paste in an oven such that the solder spheres are attached to the ball pads.

23. The method according to claim 22, wherein the rigid support is an ultrasonically deposited metal.

24. The method according to claim 22, wherein the metal is chosen from the group consisting of:

a) gold; and

b) an alloy of gold and palladium.