Wiring-design system for wiring-board for area-input/output-type semiconductor chip

• US 20030161124A1
• Filed: 02/25/2003
• Published: 08/28/2003
• Est. Priority Date: 02/26/2002
• Status: Abandoned Application

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Kariyazaki, Syuuichi
• Application Number:
  US10/372,403
• Publication Number:
  US 20030161124A1
• Time in Patent Office: Days
• US Class Current: 361/767
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

In a wiring-design system for designing a wiring-arrangement for a wiring-board on which an area-input/output type semiconductor chip is mounted, a display unit displays a lattice representing an array of pads to be provided on a chip surface of the semiconductor chip. A first layout design system defines and arranges various IO blocks on the lattice to thereby design a first layout of IO blocks thereon. A check system checks whether or not the first layout of IO blocks is properly performed in accordance with a layout rule. When the check system confirms that the first layout of IO blocks is properly performed, a second layout design system designs a second layout of IO block to be provided on the wiring-board, based on the first layout of IO blocks on the lattice. A wiring-arrangement is designed in the wiring-board concerning the second layout of IO blocks.

Claims

1. A wiring-design system for designing a wiring-arrangement for a wiring-board on which an area-input/output type semiconductor chip is mounted, which system comprises;

a display unit that displays a lattice representing an array of pads to be provided on a chip surface of said semiconductor chip;

a first layout design system that defines and arranges various IO blocks on said lattice to thereby design a first layout of IO blocks thereon;

a check system that checks whether or not said first layout of IO blocks is properly performed in accordance with a previously-prepared layout rule;

a second layout design system that designs a second layout of IO block to be provided on said wiring-board, based on said first layout of IO blocks on said lattice, when it is confirmed by said check system that said first layout of IO blocks is properly performed; and

a wiring-arrangement production system that produces a wiring-arrangement of said wiring-board with respect to said second layout of IO blocks.

2. A wiring-design system as set forth in claim 1, wherein each of said IO blocks is composed of ground pads to be connected to a ground layer of said wiring-board, electric power pads to be connected an electric power layer of said wiring board, and signal pads to be connected to a signal layer of said wiring-board.

3. A wiring-design system as set forth in claim 2, wherein said second layout design system includes a line-passage-area-definition system that defines line-passage areas with respect to each of said IO blocks on said wiring-board, with wiring-lines drawn out from the signal pads of each IO block passing through a corresponding line passage area.

4. A wiring-design system as set forth in claim 3, wherein said second layout design system further includes a geometrical-quadrilateral production system that produces a geometrical quadrilateral on said second layout of IO blocks such that the sides of said of geometrical quadrilateral are tangential to outer sides of the outermost IO blocks, and said geometrical-quadrilateral production system cooperates with said line-passage-area-definition system such that each line-passage area is defined and produced on and along a corresponding side of said geometrical quadrilateral.

5. A wiring-design system as set forth in claim 4, wherein said geometrical-quadrilateral production system produces another geometrical quadrilateral when there are remaining IO blocks provided inside said outermost IO, the production of said other geometrical quadrilateral is performed such that the sides of said other geometrical quadrilateral are tangential to outer sides of the remaining IO blocks, and said geometrical-quadrilateral production system cooperates with said line-passage-area-definition system such that each line-passage area is defined and produced on and along a corresponding side of said other geometrical quadrilateral.

6. A wiring-design system as set forth in claim 5, wherein the signal layer of said wiring-board is formed as a multi-layer structure including signal layers, a number of which corresponds to a number of said geometrical quadrilaterals, and the wiring-lines, passing through the line-passage area involved with the outermost geometrical quadrilateral are connected to the uppermost signal layer.

7. A wiring-design system as set forth in claim 1, wherein said previously-prepared layout rule comprises at least two types of layout rules, and said check system selects one of said at least two types of layout rules in accordance with design requirements of the wiring-arrangement for said wiring-board.

8. A wiring design system as set forth in claim 1, wherein said previously-prepared layout rule comprises at least two types of layout rules, one of said at least two types of layout rules being severer than the other type of layout rule, and said check system includes a determination system that determines whether two adjacent IO blocks are arranged in any one of corner areas of said lattice, and checks whether said two adjacent IO blocks are properly arranged in accordance with said one type of layout rule.