Digital multilevel non-volatile memory system

• US 20030161183A1
• Filed: 12/11/2002
• Published: 08/28/2003
• Est. Priority Date: 01/14/1999
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Tran, Hieu Van
• Granted Patent: US 6,975,539 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment reference may be used for each segment. The system may read data cells using a current sensing one or two step binary search. The system may use inverse voltage mode or inverse current mode sensing. The system may use no current multilevel sensing. The system may use memory cell replica sensing. The system may use dynamic sensing. The system may use built-in byte redundancy. Sense amplifiers capable of sub-volt (<<1V) sensing are described.

Claims

1. A method of determining data stored in a multilevel memory cell, the method comprising:

setting the memory cell in a current sensing mode;

setting a bit of the data;

dividing a reference current range into two sub-ranges to determine a divided reference value;

comparing a voltage sensed from the data cell to the divided reference value;

setting a corresponding bit based on said comparison; and

repeating said setting a bit, dividing, comparing and setting a corresponding bit for each bit of the data.

2. The method of claim 1 wherein the two sub-ranges are equal.

3. The method of claim 1 wherein the current sensing mode includes an autozero mode.

4. The method of claim 1 wherein the multilevel memory cell is a nonvolatile memory cell.

5. A method for reading a multilevel memory cell, the method comprising:

setting the memory cell in a current sensing mode;

comparing a current of the memory cell to a predetermined number of a plurality of reference values in a current range;

determining a first bit based on a comparison to a reference current of said predetermined number of reference values that is near the middle of the range and determining a second less significant bit by comparing to other of predetermined number of reference levels;

comparing the value of the data cell to reference levels in a subrange corresponding to the selected most significant bit and differing from said predetermined number of reference values; and

determining said bits based on said comparison.

6. The method of claim 5 further comprising:

ignoring some of said comparing to ones of said predetermined number of plurality of reference values based on said determined first bit.

7. The method of claim 5 wherein the current sensing mode includes an autozero mode.

8. The method of claim 5 wherein the memory cell is a nonvolatile memory cell.

9. A data storage system comprising:

a plurality of memory arrays, each memory array including a plurality of memory cells arranged in rows and columns, including a plurality of bitlines, each bitline coupling a column of said memory cells, and including a plurality of source lines, each source line coupling a portion of memory cells in a row of memory cells;

a first control circuit to apply a reference voltage on a selected bitline;

a second control circuit to apply a predetermined read bias current on a selected source line and

a read circuit to sense voltage on said selected source line and provide an output signal indicative of the content of selected memory cells in response to a sensed readout voltage on the selected source line.

10. The data storage system of claim 9 wherein the memory cells are nonvolatile memory cells.

11. The data storage system of claim 9 wherein the memory cells are multilevel nonvolatile memory cells.

12. The data storage system of claim 9 wherein the memory cells are multilevel memory cells.

13. The data storage system of claim 9 comprising an autozero circuit to couple said selected source line to an output signal of said read circuit prior to said sensed readout voltage on the selected source line.

14. A data storage system comprising:

a plurality of memory arrays, each memory array including a plurality of memory cells arranged in rows and columns, including a plurality of bitlines, and including a plurality of source lines, each bitline coupling the column of said memory cells, each source line coupling a portion of memory cells in a row of memory cells;

a first control circuit to apply a reference voltage on a selected bitline;

a second control circuit to apply a predetermined bias voltage on a selected source line; and

a read circuit to sense voltage on said selected source line and provided output signal indicative of the content of selected memory cells in response to a sensed readout voltage on the selected source line.

15. A method for determining contents of a multilevel memory cell, the method comprising:

verifying data stored in said memory cell by placing memory cell in a voltage mode; and

reading data stored in said memory cell by placing said memory cell in a current sensing mode.

16. The method of claim 15 wherein the multilevel memory cell is a nonvolatile memory cell.

17. The method of claim 15 further comprising autozeroing an output of said memory cell to an output node prior to said verifying and reading.

18. A method for determining contents of a multilevel memory cell, the method comprising:

verifying data stored in said memory cell by placing memory cell in a current sensing mode; and

reading data in said memory cell by placing memory cell in a voltage mode.

19. The method of claim 18 wherein the multilevel memory cell is a nonvolatile memory cell.

20. The method of claim 18 further comprising autozeroing and output of said memory cell to an output node prior to said verifying and reading.

21. A memory system comprising:

a plurality of memory cells arranged in a plurality of pages,

each page including a first group of memory cells arranged for storing data, and a second group of memory cells arranged for redundancy.

22. The memory system of claim 21 wherein the memory cells are nonvolatile memory cells.

23. A memory system comprising:

a plurality of memory cells arranged in a plurality of pages,

each page including a first group of memory cells arranged for storing data, a second group of memory cells arranged for redundancy, a third group of memory cells arranged to store an indicator of bad cells in said first group, and a fourth group of memory cells arranged to store a locator of said bad cells.

24. The memory system of claim 23 wherein the memory cells are nonvolatile memory cells.

25. The memory system of claim 23 wherein the memory cells are multilevel nonvolatile memory cells.

26. The memory device of claim 23 further comprising:

a decoder to address said memory cells, the decoder addressing said first group of memory cells in response to the third group of memory cells being in the first state, and the decoder addressing said first group of memory cells except for memory cells at a location indicated by said fourth group of memory cells and addressing said second group of memory cells in response to the third group of memory cells being in a second state.

27. The memory device of claim 26 further comprising:

a controller to control storing data into a page by providing address signals corresponding to the first group of memory cells to the decoder.

28. The memory device of claim 27 wherein the decoder further stores predetermined data in memory cells of the first group of memory cells corresponding to the location indicated by the fourth group of memory cells in the event that the third group of memory cells is in the second state.

29. The memory device of claim 26 further comprising a controller providing address signals corresponding to the first and second groups of memory cells to the decoder for programming and providing said address signals to the decoder for verifying data read from memory cells corresponding to said address signals.

30. The memory device of claim 29 wherein the decoder further addresses said memory cells in said first group of memory cells corresponding to the location in the fourth group of memory cells independent of whether the third group of memory cells are in said first or second states.

31. The memory device of claim 26 wherein the decoder does not address memory cells corresponding to a location indicated by the fourth group of memory cells in the event that the third group of memory cells is in a second state and a predetermined data is stored in said memory cells of the first group corresponding to the location.

32. The memory device of claim 26 further comprising a controller providing address signals corresponding to the first group of memory cells for reading a page,

wherein the decoder decodes said address signals and generates second address signals to address the first, second, third, and fourth groups of memory cells to read the contents therein and to provide the data stored in the first group of memory cells in response to the third group of memory cells being in the first state, and providing the data in the first group of memory cells except the memory cells at the location indicated by the fourth group of memory cells and the data stored in the second group of memory cells in response to the third group of memory cells being in the second state.

33. The memory device of claim 26 further comprising a controller to provide address signals corresponding to a page for erasing the first and second group of memory cells but not the third or fourth group of memory cells.

34. The memory device of claim 26 further comprising a memory to store contents of the third and fourth groups of memory cells corresponding to the page to be erased;

and

the controller to provide address signals to read the third and fourth groups of memory cells and store said read data in said memory, and providing address signals to erase the memory cells in the first, second, third, and fourth group of memory cells, and to provide address signals to store the contents in said memory into said third and fourth groups of memory cells.

35. The memory device of claim 34 wherein said memory is a latch.

36. A data storage system comprising:

a plurality of memory arrays, each memory array including a plurality of memory cells arranged in rows and columns, including a plurality of bitlines, each bitline coupling a column of said memory cells, and including a plurality of source lines, each source line coupling a row of memory cells;

a first control circuit to apply a first bias voltage on a selected source line;

a second control circuit to apply a second bias voltage on a control gate of selected memory cells;

a read circuit to sense voltage on said selected bitline and provide an output signal indicative of the content of selected memory cells in response to a sensed readout voltage on the selected bitline, wherein no read current is applied to said selected bitline.

37. A method for voltage mode reading a memory cell in a plurality of memory arrays, each memory array including a plurality of memory cells arranged in rows and columns, including a plurality of bitlines, each bitline coupling a column of said memory cells, and including a plurality of source lines, each source line coupling a row of memory cells the method comprising:

applying a first bias voltage on a selected source line;

applying a second bias voltage on a control gate of selected memory cells;

sensing a voltage on said selected bitline, without applying read current to said selected bitline; and

generating an output signal indicative of the content of selected memory cells in response to a sensed readout voltage on the selected bitline.

38. A data storage system comprising:

a plurality of memory arrays, each memory array including a plurality of memory cells arranged in rows and columns, including a plurality of bitlines, each bitline coupling a column of said memory cells, and including a plurality of source lines, each source line coupling a row of memory cells;

a first control circuit to apply a first bias voltage on a selected source line;

a second control circuit to apply a second bias voltage on a control gate of selected memory cells;

a resistive element coupled between a voltage source and a selected bitline; and

a read circuit to sense voltage on said selected bitline and provide an output signal indicative of the content of said selected memory cell in response to a sensed readout voltage on the selected bitline.

39. The data storage system of claim 38 wherein the resistive element is a resistor.

40. The data storage system of claim 38 wherein the resistive element is a transistor.

41. A method for voltage mode reading a memory cell in a plurality of memory arrays, each memory array including a plurality of memory cells arranged in rows and columns, including a plurality of bitlines, each bitline coupling a column of said memory cells, and including a plurality of source lines, each source line coupling a row of memory cells the method comprising:

applying a first bias voltage on a selected source line;

applying a second bias voltage on a control gate of selected memory cells;

applying a current through a resistive element to a selected bitline

sensing a voltage on said selected bitline; and

generating an output signal indicative of the content of selected memory cells in response to a sensed readout voltage on the selected bitline.