Device and method for comma detection and word alignment in serial transmission

• US 20030161429A1
• Filed: 11/05/2002
• Published: 08/28/2003
• Est. Priority Date: 02/22/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chiang, Chin-Yi
• Granted Patent: US 7,254,206 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines

Abstract

The invention is applied in a gigabit network environment. During the process of converting serial data into parallel data, a method is proposed to use the comma pattern in a data pipeline architecture to select word boundaries of a correct data frame from a serial bit stream. This method is further implemented in a bit receiver with a two-stage pipeline architecture to achieve the object of increasing data transmission bandwidth and efficiency.

Claims

1. A device of comma detection and word alignment for n-to-m bit conversion in serial transmission, the device comprising:

a two-stage pipeline architecture, which receives a serial data stream;

a comma detection logical circuit, which detects the distribution of a k-bit comma pattern when the serial data streams enter the first-stage pipeline in the pipeline architecture; and

a word alignment logical circuit, which extracts an n-bit word data when the serial data streams enter the second-stage pipeline in the pipeline architecture;

wherein the locations of the n-bit word data are selected according to the locations of the k-bit comma pattern, and the output data go through an n-to-m bit conversion to obtain a m-bit data.

2. The device of claim 1, wherein said pipeline architecture is comprised of D-type flip-flop.

3. The device of claim 1, wherein k<

n.

4. The device of claim 3, wherein k=7, n=10, and m=8.

5. The device of claim 1, wherein after said serial data stream enters the first-stage pipeline in the pipeline architecture, said serial data stream then flows into the second-stage pipeline of the pipeline architecture in the next period.

6. The device of claim 5, wherein said position of the n-bit word data is the position of the second-stage pipeline corresponding to the position of the first-stage k-bit comma pattern.

7. A bit receiver for n-to-m bit reception and conversion in serial transmission, the bit receiver comprising:

a pipeline architecture, which receives a serial data stream and has a first-stage pipeline and a second-stage pipeline;

a comma detection logical circuit, which detects the distribution of a k-bit comma pattern in the first-stage pipeline when the serial data stream enters the first-stage pipeline; and

a word alignment logical circuit, which extracts an n-bit word data in the second-stage pipeline when the serial data streams enter the second-stage pipeline;

wherein the locations of the n-bit word data are selected according to the position of the k-bit comma pattern in the second-stage pipeline, and the output data go through an n-to-m bit conversion to obtain a m-bit data.

8. The bit receiver of claim 7, wherein the pipeline architecture is comprised of D-type flip-flop.

9. The bit receiver of claim 7, wherein k<

n.

10. The bit receiver of claim 9, wherein k=7, n=10, and m=8.

11. The bit receiver of claim 7, wherein after said serial data stream enters the first-stage pipeline in the pipeline architecture, said serial data stream then flows into the second-stage pipeline of the pipeline architecture in the next period.

12. The bit receiver of claim 11, wherein said position of the n-bit word data is the position of the first-stage k-bit comma pattern in the second-stage pipeline.

13. A pipeline architecture with a first-stage pipeline and a second-stage pipeline for n-to-m bit receiving and conversion of a serial data stream, the pipeline architecture comprising:

a comma detection logical circuit, which detects the distribution of a k-bit comma pattern in the first-stage pipeline when the serial data stream enters the first-stage pipeline; and

a word alignment logical circuit, which extracts an n-bit word datum in the second-stage pipeline when the serial data streams enter the second-stage pipeline;

wherein the locations of the n-bit word data are selected according to the positions of the k-bit comma pattern in the second-stage pipeline, and the output data go through an n-to-m bit conversion to obtain a m-bit data.

14. The pipeline architecture of claim 13, wherein k<

n.

15. The pipeline architecture of claim 13, wherein the location of the k-bit comma pattern in the first-stage pipeline is used to define the boundaries of a corresponding n-bit data frame in the second-stage pipeline.

17. The method of claim 14, wherein k<

n.

18. The method of claim 14, wherein said location of the k-bit comma pattern in the first-stage pipeline is used to define the boundaries of a corresponding n-bit data frame in the second-stage pipeline.

19. The method of claim 18, wherein the extraction of the n-bit word data is achieved according to the n-bit boundaries of the data frame.

16. A method of comma detection and word alignment for n-to-m bit conversion in serial transmissions, the method comprising:

detecting the distribution of a k-bit comma pattern when the serial data stream enters a first-stage pipeline in a two-stage pipeline architecture; and

extracting an n-bit word data when the serial data stream enters a second-stage pipeline in the two-stage pipeline architecture;

wherein the locations of the n-bit word data are selected according to the locations of the k-bit comma pattern in the second-stage pipeline, and the output data go through an n-to-m bit conversion to obtain a m-bit data.

20. A method of comma detection and word alignment implemented in a two-stage pipeline architecture for n-to-m bit conversion in serial transmission, the method comprising:

detecting the distribution of a k-bit comma pattern in a first-stage pipeline of the two-stage the pipeline architecture; and

extracting an n-bit word data in a second-stage pipeline of the two-stage the pipeline architecture;

wherein the locations of the n-bit word data are selected according to the locations of the k-bit comma pattern in the second-stage pipeline, and the output data go through an n-to-m bit conversion to obtain a m-bit data.