Semiconductor integrated circuit and method of manufacturing the same

• US 20030162356A1
• Filed: 03/28/2003
• Published: 08/28/2003
• Est. Priority Date: 07/13/2000
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawanaka, Shigeru
• Granted Patent: US 6,898,778 B2
• Time in Patent Office: Days
• US Class Current: 438/275
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

Claims

1. A method of manufacturing a semiconductor integrated circuit comprising:

forming a plurality of voltage-activated transistors in a semiconductor layer on a substrate having an insulator at least on a surface thereof, said voltage-activated transistors including body contact regions electrically connecting one of body regions electrically isolated from each other and from said substrate and a source region and having the same channel conduction type; and

electrically connecting said voltage-activated transistors in series to a power supply terminal and an output terminal, and to said source region and said body contact region of at least said voltage-activated transistor near said output terminal, a drain region and a gate electrode of said voltage-activated transistor near said output terminal being not electrically connected.

2. A method of manufacturing a semiconductor integrated circuit comprising:

storing a cell library in a database, said cell library containing data of at least a plurality of voltage-activated transistors electrically connected in series and in which a body region and a source region of at least said voltage-activated transistor near an output terminal are electrically connected and have the same potential;

designing a logic circuit;

locating said cell library from said database to a memory space on the basis of said logic circuit by using a design automation system; and

linking said cell library in said memory space using said design automation system and creating logic circuit data.

3. A method of claim 2, wherein a drain region and a gate electrode of said voltage-activated transistor near said output terminal are not electrically connected.

4. A method of claim 2 further comprising making a manufacturing mask on the basis of said logic circuit data created by said design automation system.

5. A method of claim 3 further comprising making a manufacturing mask on the basis of said logic circuit data created by said design automation system.

6. A method of claim 2 further comprising forming a logic circuit in a semiconductor layer on a substrate having an insulator at least on a surface thereof and manufacturing a semiconductor integrated circuit.

7. A method of claim 3 further comprising forming a logic circuit in a semiconductor layer on a substrate having an insulator at least on a surface thereof and manufacturing a semiconductor integrated circuit.

8. A method of claim 4 further comprising forming a logic circuit by using said manufacturing mask in a semiconductor layer on a substrate having an insulator at least on a surface thereof and manufacturing a semiconductor integrated circuit.

9. A method of claim 5 further comprising forming a logic circuit by using said manufacturing mask in a semiconductor layer on a substrate having an insulator at least on a surface thereof and manufacturing a semiconductor integrated circuit.

10. A method of manufacturing a semiconductor integrated circuit comprising:

storing a cell library in a database, said cell library containing data of at least a plurality of first voltage-activated transistors having the same channel conduction type, electrically connected in parallel or in series between a first power supply terminal and an output terminal, and a body region and a source region of at least said first voltage-activated transistor near said output terminal are electrically connected and have the same potential, and a plurality of second voltage-activated transistors having the same channel conduction type, electrically connected in series or in parallel to a second power supply terminal and said output terminal, and a body region and a source region of at least said second voltage-activated transistor near said output terminal are electrically connected and have the same potential;

designing a logic circuit;

locating said cell library from said database to a memory space on the basis of said logic circuit by using a design automation system; and

linking said cell library in said memory space using said design automation system and creating logic circuit data.

11. A method of manufacturing a semiconductor integrated circuit comprising:

storing a cell library in a database, said cell library containing data of at least first and second voltage-activated transistors having the same channel conduction type, electrically connected in series between a first power supply terminal and a second power supply terminal of which potential is higher than that of said first power supply terminal, a body region and a source region of at least said first or second voltage-activated transistor near said second power supply terminal being electrically connected and have the same potential;

designing a logic circuit;

locating said cell library from said database to a memory space on the basis of said logic circuit by using a design automation system; and

linking said cell library in said memory space using said design automation system and creating logic circuit data.