Shared bypass bus structure

• US 20030163649A1
• Filed: 02/05/2003
• Published: 08/28/2003
• Est. Priority Date: 02/25/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cheng, Kai, Hoogland, Robert J., Kapur, Suvansh K.
• Granted Patent: US 6,912,612 B2
• Time in Patent Office: Days
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/082 Associative directories G06F12/0822 takes precedence
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0862 with prefetch

Abstract

A shared bypass bus structure for low-latency coherency controller access in a coherent scalable switch. In a coherent scalable switch with multiple coherent interconnect ports, distributed coherency control structures, and a crossbar interface between them, a shared bypass bus permits data transfer between the coherent interconnect ports and the coherency control structures while bypassing the crossbar interface. Some embodiments may comprise scalable switches to support one or more sets of processors with substantially independent snoop or cache coherency paths or arrangements.

Claims

1. An apparatus, comprising:

a bypass bus structure coupled between a first coherent interconnect port and a coherency control structure to transmit data for a cache coherency operation substantially independent of transmission with a crossbar structure coupled to the first coherent interconnect port; and

an arbitrator coupled with the bypass bus structure to coordinate transmission of the data between the first coherent interconnect port and the coherency control structure.

2. The apparatus of claim 1, wherein the bypass bus structure comprises a multiplexing structure to transmit more than one transaction on the bypass bus structure.

3. The apparatus of claim 1, wherein the bypass bus structure comprises an incoming bus and an outgoing bus.

4. The apparatus of claim 1, wherein the first coherent interconnect port is coupled with a downbound snoop path and a second coherent interconnect port is coupled with a scalable node controller.

5. The apparatus of claim 1, wherein the bypass bus structure comprises a remote bus structure and a local bus structure.

6. A system, comprising:

a memory;

a controller circuit coupled to the memory and comprising

a plurality of coherent interconnect ports;

a crossbar structure coupled with each of the coherent interconnect ports to transfer data between any two of the plurality of coherent interconnect ports;

a plurality of coherency control structures;

a bypass bus structure coupled with the plurality of coherency control structures and with the plurality of coherent interconnect ports to transfer data between any of the plurality of coherency control structures and any of the plurality of coherent interconnect ports substantially independent from a transfer through the crossbar structure.

7. The system of claim 6, further comprising a multiplexing structure coupled with the bypass bus structure to transmit a plurality of transactions on the bypass bus structure substantially concurrently.

8. The system of claim 6, wherein said bypass bus structure comprises an incoming bus and an outgoing bus.

9. The system of claim 8, wherein the incoming bus is coupled to a first multiplexer to selectively couple each of multiple ones of the coherent interconnect ports to the incoming bus, and the outgoing bus is coupled to a second multiplexer to selectively couple each of the multiple ones of the coherent interconnect ports to the outgoing bus.

10. The system of claim 6, wherein a first coherent interconnect port of the plurality of coherent interconnect ports is coupled with a downbound snoop path and a second coherent interconnect port of the plurality of coherent interconnect ports is coupled with a scalable node controller.

11. The system of claim 6, wherein the bypass bus structure comprises a local bus structure coupled to a first coherency control structure and to a first coherent interconnect port in a same region as the first coherency control structure, and a remote bus structure coupled to a second coherency control structure and a second coherent interconnect port in a different region as the first coherency control structure.

12. A method, comprising:

receiving a snoop request at a first port of a coherent interconnect port switch;

receiving a second request at a second port of the coherent interconnect port switch;

transmitting the second request to a third port of the coherent interconnect port switch; and

transmitting the snoop request to a coherency control structure of the coherent interconnect port switch substantially simultaneously with said transmitting the second request to the third port.

13. The method of claim 12, wherein said transmitting the second request to a third port is substantially independent from said transmitting the snoop request.

14. The method of claim 12, wherein said transmitting the snoop request comprises bypassing a structure to transmit the second request.

15. The method of claim 14, wherein said bypassing a structure comprises bypassing a crossbar structure.