Method and apparatus for translating guest physical addresses in a virtual machine environment

• US 20030163662A1
• Filed: 02/25/2002
• Published: 08/28/2003
• Est. Priority Date: 02/25/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Neiger, Gilbert, Uhlig, Richard, Kozuch, Michael A., Smith, Lawrence O. III, Glew, Andy, Boleyn, Erich S.
• Granted Patent: US 7,124,273 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

A method and an apparatus are used to efficiently translate memory addresses. The translation scheme yields a translated address, a memory type for the translated address, and a fault bit for the translation.

Claims

1. A method comprising:

dividing a physical address space into a plurality of segments;

computing an interim first address from a physical address from the physical address space;

computing an interim base value from a base value associated with the physical address;

comparing the interim first address and the interim base value to determine whether the physical address can be validly translated to obtain a translated address; and

if the physical address can be validly translated, combining the physical address with an offset value to obtain the translated address.

2. The method of claim 1, further comprising:

determining a memory type of the translated address.

3. The method of claim 2, wherein determining comprises:

reading the memory type from the base value associated with the physical address.

4. The method of claim 1, wherein computing the interim first address comprises:

determining which bits of the physical address should be retained in the interim first address for comparison with the interim base value,

and wherein computing the interim base value comprises;

determining which bits of a base value should be retained in the interim base value for comparison with the interim first address.

5. The method of claim 4, wherein determining which bits of the physical address and which bits of the base value should be retained for comparison comprises:

applying a mask value to each of the physical address and the base value, the mask value associated with the physical address.

6. The method of claim 1, wherein combining comprises:

determining which bits of the physical address should be retained in the translated address; and

substituting bits from the offset value for bits of the physical address which are not to be retained in the translated address.

7. The method of claim 6, wherein determining which bits comprises:

applying a mask value to the physical address, the mask value associated with the physical address.

8. The method of claim 1, further comprising:

issuing a fault alert.

9. The method of claim 8, wherein issuing the fault alert comprises:

issuing a notice that no mapping exists for the physical address.

10. The method of claim 8, wherein issuing the fault alert comprises:

issuing a notice that an attempt has been made to access a particular segment.

11. The method of claim 10, wherein issuing the notice comprises:

detecting whether a fault bit has been set for the particular segment.

12. The method of claim 1, wherein if the physical address cannot be validly translated, the translated address is the same as the physical address.

13. An apparatus comprising:

a memory having a first address space divided into a plurality of segments;

comparison logic circuitry coupled to the memory to create an interim first address from a first address from one of the plurality of segments, to create an interim base value, and to compare the interim first address and the interim base value to determine whether the first address belongs to a segment that can be validly translated to obtain a second address; and

combination logic circuitry coupled to the comparison logic circuitry and to the memory, the combination logic circuitry to combine the first address with an offset value to obtain the second address if the comparison logic circuitry indicates that the first address can be validly translated.

14. The apparatus of claim 13, wherein the comparison logic circuitry comprises:

masking circuitry to apply a mask value to the first address to obtain the interim first address and to apply the mask value to a base value to obtain the interim base value, the mask value associated with the first address.

15. The apparatus of claim 13, wherein the combination logic circuitry comprises:

masking circuitry to apply a mask value to the first address to determine which bits of the first address should be retained in the second address; and

substitution circuitry to substitute bits from the offset value for bits of the first address which are not to be retained in the second address.

16. The apparatus of claim 13, further comprising:

fault detection circuitry coupled to the comparison logic circuitry, the fault detection circuitry to detect and issue fault alerts.

17. A system comprising:

a processor;

memory coupled to the processor, the memory having a first address space divided into a plurality of segments;

comparison logic circuitry coupled to the memory to create an interim first address from a first address from one of the plurality of segments, to create an interim base value, and to compare the interim first address and the interim base value to determine whether the first address belongs to a segment that can be validly translated to obtain a second address; and

combination logic circuitry coupled to the comparison logic circuitry and to the memory, the combination logic circuitry to combine the first address with an offset value to obtain the second address if the comparison logic circuitry indicates that the first address can be validly translated.

18. The system of claim 17, wherein the comparison logic circuitry comprises:

masking circuitry to apply a mask value to the first address to obtain the interim first address and to apply the mask value to a base value to obtain the interim base value, the mask value associated with the first address.

19. The system of claim 17, wherein the combination logic circuitry comprises:

masking circuitry to apply a mask value to the first address to determine which bits of the first address should be retained in the second address; and

substitution circuitry to substitute bits from the offset value for bits of the first address which are not to be retained in the second address.

20. The system of claim 17, further comprising:

fault detection circuitry coupled to the comparison logic circuitry, the fault detection circuitry to detect and issue fault alerts.