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System and method for identifying and eliminating bottlenecks in integrated circuit designs

  • US 20030163797A1
  • Filed: 02/27/2002
  • Published: 08/28/2003
  • Est. Priority Date: 02/27/2002
  • Status: Active Grant
First Claim
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1. A method of integrated circuit design, said method comprising the steps of:

  • a) identifying critical paths in an integrated circuit design;

    b) weighting edges in identified said critical paths c) assigning net criticality to each weighted edge responsive to edge weight; and

    d) re-placing and wiring nets according to edge criticality.

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