Wafer processing apparatus and a wafer stage and a wafer processing method

• US 20030164226A1
• Filed: 03/04/2002
• Published: 09/04/2003
• Est. Priority Date: 03/04/2002
• Status: Active Grant

• Current Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Original Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Inventors: Kanno, Seiichiro, Kanai, Saburou, Masuda, Toshio, Suehiro, Mitsuru, Kawahara, Hironobu
• Granted Patent: US 6,677,167 B2
• Time in Patent Office: Days
• US Class Current: 156/345.51
• CPC Class Codes: H01L 21/67109 mainly by convection

Abstract

A wafer processing apparatus comprising a wafer stage, wherein a semiconductor wafer is mounted on the wafer stage so as to process the semiconductor wafer, wherein a holding mechanism of the wafer stage is commonly used for a plurality of wafer stages, and accordingly, the wafer stage can be changed into a wafer stage having a different function so as to process the semiconductor wafer.

Claims

1. A wafer processing apparatus comprising a wafer and in which a semiconductor wafer is set on the wafer stage so as to be processed, wherein a holding mechanism of the wafer stage is commonly used among a plurality of wafer stages, and the wafer stage is changed into a wafer stage having a different function so as to process the wafer.

8. A wafer processing apparatus as claimed in any one of claims 1 to 5, wherein the wafer stage is formed on its outer surface with a dielectric film, and by effecting a potential difference between the dielectric film and the semiconductor wafer so that the semiconductor wafer is secured to the wafer stage by an electrostatic force.

9. A wafer processing apparatus as claimed in claim 8, wherein the dielectric film is formed of a sintered material composed of ceramic as a main component.

10. A wafer processing apparatus as claimed in claim 9, wherein the dielectric film is secured to the wafer stage through either a joint by an electrically conductive blazing material or a joint by an adhesive.

11. A wafer processing apparatus as claimed in claim 8, wherein the dielectric film is a film formed by a chemical vapor phase growth process and made of ceramic as a main component.

12. A wafer processing apparatus as claimed in claim 8, wherein the dielectric film is a film formed by spay coating and made of ceramic as a main component.

2. A wafer processing apparatus in which a semiconductor wafer is set on a wafer stage so as to be processed, wherein the wafer stage can be separated from a holding part of the wafer stage, and in order to enable a wafer stage having a different stage to be commonly installed to the holding part, a mechanism for securing the wafer stage to the holding part and a mechanism which requires alignment between the holding part and the wafer stage are commonly used among the plurality of wafer stages.

3. A wafer processing apparatus as claimed in claim 2, wherein the wafer stage comprises a base and a lower cover, the base is formed in its lower surface with a temperature adjusting groove, and the lower cover is joined to the lower surface of the base.

4. A wafer processing apparatus as claimed in claim 2, wherein the wafer stage is formed of a base formed in its lower surface with a temperature adjusting groove, and the base is jointed at its lower surface to the holding part through the intermediary of an O-ring.

5. A wafer processing apparatus in which a semiconductor wafer is set on an upper surface of a wafer stage and is then processed, wherein the wafer stage comprises therein a heat insulation part having a thermal conductivity which is smaller than that of a material of the wafer stage, and a temperature adjusting groove for circulating a temperature adjusting medium therethrough in order to cool or heat the wafer stage.

6. A wafer processing apparatus as claimed in claim 5, wherein the temperature adjusting groove is provided only on either one of the inside and the outside of the heat insulation part.

7. A wafer processing apparatus as claimed in claim 5, wherein the temperature adjusting groove is formed on each of the inside and the outside of the heat insulation part.

13. A wafer stage mounted in a wafer processing apparatus, and for carrying thereon a semiconductor wafer so as to process the semiconductor wafer, wherein the wafer stage has an attaching part for attachment to the wafer processing apparatus, which is commonly used among a plurality of wafer stages, and is configured to cope with a change of the wafer stage into a wafer stage having a different function.

14. A wafer stage as claimed in claim 13, wherein the water stage is configured to enable the wafer stage to be separated from a structure to which the wafer stage is secured, in order to mount any of a plurality of wafer stages having different functions on the structure, a means for securing the wafer stage to the structure, a component part which requires alignment between the structure and the wafer stage, or a structure part is commonly used among a plurality of wafer stages.

15. A wafer stage as claimed in claim 14, wherein the component part or the structure part are an electrical connection structure, a semiconductor wafer transfer mechanism, and a cooling structure for the wafer stage, a through hole for introducing cooling gas between the semiconductor wafer and the wafer stage, or a semiconductor wafer monitor mechanism.

16. A wafer stage as set forth in claim 14, wherein the wafer stage is composed of a base formed therein with a temperature adjusting groove for circulating temperature adjusting medium therethrough in order to cool or heat the wafer stage;

and a lower cover joined to the base on the temperature adjusting groove side.

25. A method of processing a wafer, incorporating a processing chamber for subjecting a semiconductor wafer to a plasma process, means for generating plasma in the processing chamber, and a wafer stage for carrying thereon the semiconductor wafer so as to subject the semiconductor wafer to the plasma process, wherein said wafer stage is as set forth in any one of claims 13 to 24, and a high frequency voltage for apply a bias voltage to the semiconductor wafer, and a D.C. voltage for effecting a potential difference between the semiconductor wafer and the wafer stage are applied to the wafer stage.

26. A method of processing a wafer, incorporating a processing chamber for subjecting a semiconductor wafer to a plasma process, a means for generating plasma in the processing chamber, and a wafer stage for carrying thereon the semiconductor wafer so as to subject the semiconductor wafer to the plasma process, wherein said wafer stage is as set forth in any one of claims 16 to 24, a high frequency voltage for applying a bias he semiconductor wafer, and a D.C. voltage for effecting a potential difference between the semiconductor wafer and the wafer stage are applied to the wafer stage, and temperature adjusting medium is circulated through the temperature adjusting groove formed in the wafer stage so as to control the temperature of the wafer stage.

27. A method as claimed in claim 25 or 26, wherein the temperature of the semiconductor wafer, the temperature of the temperature adjusting medium and the temperature of the wafer stage are monitored in order to control the wafer process.

17. A wafer stage for processing a semiconductor wafer, wherein the wafer stage comprises a heat insulation layer and a temperature adjusting groove, the heat insulation layer is made of a material having a thermal conductivity which is smaller than that of a material of the wafer stage;

the temperature adjusting groove is adapted to circulate temperature adjusting medium therethrough so as to cool or heat the wafer stage.

18. A wafer stage as claimed in claim 17, wherein the temperature adjusting groove is formed only on either the inside or the outside of the heat insulating layer.

19. A wafer stage as claimed in claim 17, wherein the temperature adjusting groove is provided in each of the inside and the outside of the heat insulation layer.

20. A wafer stage as claimed in claim 17, wherein a dielectric film is formed on the outer surface of the wafer stage, and an electrical potential difference is effected between the dielectric film and the semiconductor wafer so as to produce an electrostatic chuck function for fixing the semiconductor wafer with a static electric force.

21. A wafer stage as claimed in claim 20, wherein the dielectric film is formed of a sintered material comprising a ceramic as a main component.

22. A wafer stage as claimed in claim 20, wherein the dielectric film is secured through either a joint by an electrically conductive blazing material or a joint by an adhesive.

23. A wafer stage as claimed in claim 20, wherein said dielectric film is a film formed by a chemical vapor phase growth process and made of ceramic as a main component.

24. A wafer stage as claimed in claim 20, wherein the dielectric film is a film formed by spray coating, and made of ceramic as a main component.