Differential clock signal detection circuit

• US 20030164720A1
• Filed: 03/03/2003
• Published: 09/04/2003
• Est. Priority Date: 03/01/2002
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: ICS Technologies, Inc.
• Inventors: Self, Paul W.
• Granted Patent: US 6,977,529 B2
• Time in Patent Office: Days
• US Class Current: 327/77
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H03K 5/19 Monitoring patterns of pulse trains indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop

Abstract

A semiconductor integrated circuit includes a first clock input and a second clock input to receive elements of a differential clock signal. Each clock signal element has a logic state. The circuit generates an output activation signal that depends on the states of the differential clock input signals. Operation of the circuit does not require detection of a frequency of the differential clock signal.

Claims

1. A semiconductor integrated circuit comprising:

a first input that receives a first element of a differential clock signal, the first element having a first logic state; and

a second input that receives a second element of the differential clock signal, the second element having a second logic state;

wherein the circuit generates an output that exhibits a predetermined output state when the states of the first and second elements of the differential clock signal satisfy a predetermined logic state; and

wherein the output is electrically connected to an activation input of a device that also receives the differential clock signal.

8. The circuit of claim 1 wherein the first input is electrically connected to an input of a first voltage comparator having an output and the second input is electrically connected to an input of a second voltage comparator having an output.

9. The circuit of claim 8 wherein each voltage comparator determines whether its corresponding input signal exhibits a logic state that is below a voltage threshold, the voltage threshold being no more than one half of a reference voltage of the comparator.

10. The circuit of claim 9 wherein the output of the first voltage comparator and the output of the second voltage comparator are electrically connected to inputs of an AND gate.

11. The circuit of claim 1 wherein the first input is electrically connected to a first CMOS inverter having an output and the second input is electrically connected to a second CMOS inverter having an output.

12. The circuit of claim 1 wherein operation of the circuit does not require detection of a frequency of the differential clock signal.

2. The circuit of claim I further comprising a comparing circuit having a voltage threshold, so that the comparing circuit determines whether one or more of the first logic state and the second logic state correspond to a signal that is below the voltage threshold.

3. The circuit of claim 2 wherein the comparing circuit comprises a pair of voltage comparators.

4. The circuit of claim 3 wherein each voltage comparator has a reference voltage, and the voltage threshold is less than one-half of the reference voltage.

5. The circuit of claim 2 wherein the comparing circuit comprises a pair of CMOS inverters, wherein each CMOS inverter includes a p-channel transistor and an n-channel transistor, wherein each of the p-channel transistors exhibits a strength that is less than a strength of its corresponding n-channel transistor.

7. The circuit of claim 6 wherein each CMOS inverter has a switching threshold, and each CMOS inverter determines whether its corresponding input signal exhibits a logic state that is below the switching threshold.

13. A semiconductor integrated circuit comprising:

a first input that receives a first element of a differential clock signal, the first element having a first logic state;

a second input that receives a second element of the differential clock signal, the second element having a second logic state; and

a comparing circuit having a voltage threshold, wherein the comparing circuit determines whether one or more of the first logic state and the second logic state correspond to a signal that is below the voltage threshold;

wherein the circuit generates an output that exhibits a predetermined output state when each of the first and second logic states are below the voltage threshold.

14. The circuit of claim 13 wherein the output is electrically connected to an activation input of a device that also receives the differential clock signal.

15. A semiconductor integrated circuit comprising:

a first clock input that receives a first element of a differential clock signal, the first element having a first logic state;

a second clock input that receives a second element of the differential clock signal, the second element having a second logic state;

a first comparator having a comparator input that is electrically connected to the first clock input; and

a second comparator having a comparator input that is electrically connected to the second clock input;

wherein each comparator determines whether its corresponding clock signal exhibits a logic state that is below a voltage threshold, the voltage threshold being no more than one half of a reference voltage of the comparator.

16. The circuit of claim 15 wherein the circuit generates an output that exhibits a predetermined output state when each of the first and second logic states is below the voltage threshold.

17. The circuit of claim 16 wherein the output is electrically connected to an activation input of a device that also receives the differential clock signal.

18. A semiconductor integrated circuit, comprising

a first input that receives a first element of a differential clock signal, the first element having a first logic state;

a second input that receives a second element of the differential clock signal, the second element having a second logic state; and

an output that issues a control signal that is responsive to detection of the first logic state and the second logic state together being outside of normal operation of the differential clock signal.

19. A semiconductor integrated circuit, comprising

a first input pair, wherein each input in the first input pair receives an element of a differential clock signal, wherein each element of the differential clock signal exhibits a logic state;

at least one additional input pair, wherein each additional input pair receives an additional differential clock signal, wherein each additional differential clock signal has a pair of elements, each of which exhibits a logic state; and

an output that issues a control signal that is responsive to detection of the logic states of at least one of the differential clock signals being outside of normal operation of the differential clock signal.

20. A method of generating an activation signal comprising:

receiving a first element of a differential clock signal;

receiving a second element of the differential clock signal;

comparing a logic state of the first element to a reference voltage and generating a first signal corresponding to the logic state of the first element;

comparing a logic state of the second element to a reference voltage and generating a second signal corresponding to the logic state of the second element; and

generating an output signal that relates to the logic states of the first and second elements.

21. The method of claim 20 further comprising using the output signal to initiate an action by a device that also receives the differential clock signal.

22. A method of generating an activation signal comprising:

receiving a first element of a differential clock signal;

receiving a second element of the differential clock signal;

determining whether the first element exhibits a logic state that is below a threshold and generating a first signal corresponding to the logic state of the first element;

determining whether the second element exhibits a logic state that is below a threshold and generating a second signal corresponding to the logic state of the second element; and

generating an output signal that relates to the logic states of the first and second elements.

23. The method of claim 22 further comprising using the output signal to initiate an action by a device that also receives the differential clock signal.

24. A method of generating an activation signal comprising:

receiving a first element of a differential clock signal;

receiving a second element of a differential clock signal; and

generating an activation signal that is dependent upon whether the first element and the second element are together within normal operation of the clock signal.