Microcomputer capable of identifying instruction executed at abnormal event

• US 20030167424A1
• Filed: 08/26/2002
• Published: 09/04/2003
• Est. Priority Date: 03/01/2002
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Hori, Yoshihisa, Konishi, Masayuki, Miura, Hiromichi
• Application Number:
  US10/227,277
• Publication Number:
  US 20030167424A1
• Time in Patent Office: Days
• US Class Current: 714/47
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory
• CPC Class Codes: G11C 2029/5606 Error catch memory

Abstract

A microcomputer including a test-only RAM, a WDT (watchdog timer) and a clock controller. The test-only RAM stores information present on the address bus and data bus during the operation in a single-chip mode. The WDT counts a specified time interval according to a stored-ROM program in such a manner that it does not underflow. If the WDT underflows during the operation in the single-chip mode, it makes a decision that an abnormal event occurs, and outputs an underflow signal. The clock controller halts writing the address bus information and data bus information into the test-only RAM in response to the underflow signal. The microcomputer can easily identify an instruction which is being executed when a malfunction such as runaway occurs in the single-chip mode.

Claims

1. A microcomputer comprising:

a storage installed in a chip for storing a stored program executed in a single-chip mode;

a test-only memory for sequentially storing address bus information and data bus information present on an address bus and data bus during operation based on the stored program;

an abnormal event detector for detecting an abnormal event in the operation based on the stored program, and for producing an abnormal event detection signal; and

a controller for halting writing the address bus information and data bus information into said test-only memory after the abnormal event in response to the abnormal event detection signal fed from said abnormal event detector.

2. The microcomputer according to claim 1, wherein said abnormal event detector consists of a counter for continuously counting a specified time interval in synchronization with a start instruction of the stored program, and wherein said counter produces the abnormal event detection signal by making a decision that the abnormal event occurs in the operation based on the stored program if the counting of the specified time interval becomes irregular.

3. The microcomputer according to claim 1, wherein said test-only memory has a memory capacity for storing the address bus information and data bus information of at least one instruction of the stored program, and successively writes the latest address bus information and data bus information over existing information during the operation based on the stored program.

4. The microcomputer according to claim 1, wherein said test-only memory starts storing the address bus information and data bus information in response to a test-mode entry signal that indicates a start point of abnormal event detection of the stored program.

5. The microcomputer according to claim 4, further comprising a test mode setting port for inputting the test-mode entry signal from an outside of the chip.

6. The microcomputer according to claim 4, further comprising a test mode setting register for setting the test-mode entry signal.

7. The microcomputer according to claim 6, wherein the test-mode entry signal includes area selection information that designates which one of said test-only memory and said test mode setting register should store the address bus information and data bus information, and wherein a CPU of said microcomputer decides a stored address of the address bus information and data bus information in accordance with the area selection information.

8. A microcomputer comprising:

a storage installed in a chip for storing a stored program executed in a single-chip mode;

a test mode setting register for setting a test-mode entry signal that indicates a starting time point of abnormal event detection of the stored program;

a CPU for successively writing address bus information and data bus information present on an address bus and data bus during operation based on the stored program at least into an unused area of said test mode setting register in response to a test-mode entry signal placed in said test mode setting register;

an abnormal event detector for detecting an abnormal event in the operation based on the stored program, and for producing an abnormal event detection signal; and

a controller for halting writing the address bus information and data bus information into the unused area of said test mode setting register after the abnormal event in response to the abnormal event detection signal fed from said abnormal event detector.

9. The microcomputer according to claim 8, wherein said CPU successively writes the address bus information and data bus information present on the address bus and data bus during the operation based on the stored program into an entire area of said test mode setting register, when the test-mode entry signal is placed in said test mode setting register, and the abnormal event detection of the stored program is started.