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Microcomputer capable of identifying instruction executed at abnormal event

  • US 20030167424A1
  • Filed: 08/26/2002
  • Published: 09/04/2003
  • Est. Priority Date: 03/01/2002
  • Status: Abandoned Application
First Claim
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1. A microcomputer comprising:

  • a storage installed in a chip for storing a stored program executed in a single-chip mode;

    a test-only memory for sequentially storing address bus information and data bus information present on an address bus and data bus during operation based on the stored program;

    an abnormal event detector for detecting an abnormal event in the operation based on the stored program, and for producing an abnormal event detection signal; and

    a controller for halting writing the address bus information and data bus information into said test-only memory after the abnormal event in response to the abnormal event detection signal fed from said abnormal event detector.

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