Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

• US 20030168680A1
• Filed: 03/11/2002
• Published: 09/11/2003
• Est. Priority Date: 03/11/2002
• Status: Active Grant

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Monolithic System Technology
• Inventors: Hsu, Fu-Chieh
• Granted Patent: US 6,686,624 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A vertical one-transistor, floating-body DRAM cell is fabricated by forming an isolation region in a semiconductor substrate, thereby defining a semiconductor island in the substrate. A buried source region is formed in the substrate, wherein the top/bottom interfaces of the buried source region are located above/below the bottom of the isolation region, respectively. A recessed region is etched into the isolation region, thereby exposing sidewalls of the semiconductor island, which extend below the top interface of the buried source region. A gate dielectric is formed over the exposed sidewalls, and a gate electrode is formed in the recessed region, over the gate dielectric. A drain region is formed at the upper surface of the semiconductor island region, thereby forming a floating body region between the drain region and the buried source region. Dielectric spacers are formed adjacent to the gate electrode, thereby covering exposed edges of the gate dielectric.

Claims

1. A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell comprising:

a semiconductor island region including a drain region, a floating body region and a buried source region located a vertical configuration;

an isolation region surrounding the semiconductor island region;

a recessed region located in the isolation region adjacent to the semiconductor island region, wherein the recessed region exposes a sidewall region of the semiconductor island region; and

a gate dielectric layer located on the sidewall region, wherein the floating body region is isolated by the drain region, the buried source region, the isolation region, and the gate dielectric layer.

2. The 1T/FB DRAM cell of claim 1, wherein the isolation region is a shallow trench isolation (STI) region.

3. The 1T/FB DRAM cell of claim 1, further comprising a gate electrode located in the recessed region and contacting the gate dielectric layer.

4. The 1T/FB DRAM cell of claim 3, wherein a portion of the gate electrode extends over an upper surface of the isolation region.

5. The 1T/FB DRAM cell of claim 4, further comprising a dielectric spacer located adjacent to the gate electrode, wherein the dielectric spacer extends over the gate dielectric layer at an upper surface of the semiconductor island region.

6. The 1T/FB DRAM cell of claim 1, wherein the buried source region has a top interface located above a lower edge of the isolation region, and a bottom interface located below the lower edge of the isolation region.

7. The 1T/FB DRAM cell of claim 6, wherein the drain region is located at an upper surface of the semiconductor island region.

8. The 1T/FB DRAM cell of claim 7, wherein the floating body region is located in the semiconductor island region between the drain region and the buried source region.

9. The 1T/FB DRAM cell of claim 1, wherein the recessed region extends a first depth into, but not completely through, the isolation region.

10. The 1T/FB DRAM cell of claim 9, wherein the buried source region has a top interface located above the first depth.

11. The 1T/FB DRAM cell of claim 1, further comprising a bias voltage source coupled to the buried source region.

12. The 1T/FB DRAM cell of claim 1, wherein the buried source region is grounded.

13. The 1T/FB DRAM cell of claim 1, wherein the buried source region is formed by ion implantation.

14. The 1T/FB DRAM cell of claim 1, wherein the buried source region and the drain region have a first conductivity, and the floating body region has a second conductivity type.

15. The 1T/FB DRAM cell of claim 14, wherein the first conductivity type is N-type, and the second conductivity type is P-type.

16. The 1T/FB DRAM cell of claim 14, further comprising a deep well region of the first conductivity type located below and continuous with the buried source region.

17. The 1T/FB DRAM cell of claim 14, further comprising a well region of the first conductivity type continuous with the buried source region.

18. The 1T/FB DRAM cell of claim 1, wherein the buried source region, the drain region and the floating body region contact the gate dielectric layer.

19. The 1T/FB DRAM cell of claim 1, wherein the sidewall region includes a plurality of sidewalls extending around the semiconductor island region.

20. The 1T/FB DRAM cell of claim 19, wherein the semiconductor island region has a polygonal shape, wherein the sidewall region is located along two or more sidewalls of the polygonal shape.

21. A method of operating a vertical one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell having a buried source region, the method comprising:

biasing the buried source region; and

writing a data bit to the 1T/FB DRAM cell using a hot carrier injection mechanism.

22. A method of operating a vertical one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell having a buried source region, the method comprising:

biasing the buried source region; and

writing a data bit to the 1T/FB DRAM cell using a junction forward bias mechanism.

23. A method of fabricating a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell, method comprising:

forming a shallow trench isolation (STI) region in a semiconductor substrate, wherein the STI region defines a semiconductor island region in the semiconductor substrate, and wherein the STI region extends a first depth below an upper surface of the semiconductor substrate; and

forming a buried source region having a first conductivity type below the upper surface of the semiconductor substrate, the buried source region having a top interface located below the upper surface of the semiconductor substrate and above the first depth, and a bottom interface located below the first depth.

24. The method of claim 23, wherein the buried source region is formed by an ion implantation step.

25. The method of claim 23, further comprising performing a threshold voltage adjustment implant having the second conductivity type into the semiconductor island region.

26. The method of claim 23, further comprising etching a recessed region in the STI region adjacent to the semiconductor island region, wherein the recessed region extends a second depth below the upper surface of the substrate, the second depth being less than the first depth, and the top interface of the source region being located above the second depth.

27. The method of claim 26, wherein the step of etching the recessed region exposes one or more sidewalls of the semiconductor island region.

28. The method of claim 27, further comprising forming a gate dielectric layer over the one or more exposed sidewalls of the semiconductor island region.

29. The method of claim 27, further comprising forming a gate electrode in the recessed region over the gate dielectric layer.

30. The method of claim 29, further comprising forming a drain region of the first conductivity type in the semiconductor island region, wherein the drain region is continuous with the upper surface of the semiconductor substrate.

31. The method of claim 30, wherein a floating body region of the second conductivity type is formed between the drain region and the buried source region in the semiconductor island region.

32. The method of claim 30, wherein a first portion of the gate electrode is located over the upper surface of the semiconductor substrate, the method further comprising forming a dielectric spacer adjacent to the first portion of the gate electrode, wherein the dielectric spacer extends over a portion of the gate dielectric layer at the upper surface of the semiconductor substrate.

33. The method of claim 23, wherein the 1T/FB DRAM cell is fabricated using a process compatible with a standard CMOS process.

34. The method of claim 23, further comprising forming a well region having the first conductivity type in the semiconductor substrate, wherein the buried source region contacts the well region.

35. The method of claim 23, further comprising forming a deep well region having the first conductivity type in the semiconductor substrate, wherein the deep well region is located below and continuous with the buried source region.

36. The method of claim 35, further comprising forming a well region having the first conductivity type in the semiconductor substrate, wherein the well region contacts the deep well region.