Vertical MOSFET with horizontally graded channel doping

• US 20030168687A1
• Filed: 03/11/2002
• Published: 09/11/2003
• Est. Priority Date: 03/11/2002
• Status: Active Grant

• Current Assignee: Qimonda AG (Infineon Technologies AG), International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rengarajan, Rajesh, Chidambarrao, Dureseti, Lee, Kil-Ho, Mandelman, Jack A., McStay, Kevin
• Granted Patent: US 6,740,920 B2
• Time in Patent Office: Days
• US Class Current: 257/300
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench

Abstract

Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants—an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.

Claims

1. A vertical transistor formed in a semiconductor substrate comprising:

a upper transistor electrode formed in a top level of said transistor;

a lower transistor electrode formed in a lower level of said transistor;

a gate dielectric extending downwardly from said upper transistor electrode toward said lower transistor electrode and abutting a transistor body formed in said semiconductor substrate;

a threshold dopant distribution of dopant disposed in said semiconductor body, said dopant distribution having a peak adjacent said gate dielectric and a lower value of dopant concentration away from said gate dielectric; and

a transistor gate disposed adjacent said gate dielectric on a side opposite said transistor body.

2. A transistor according to claim 1, in which said threshold dopant distribution has a first lateral peak value in an upper portion of said transistor body and a second lateral peak value lower than said first lateral peak value in a lower portion of said body, whereby said concentration value of said threshold dopant distribution in said channel has a minimum value near said lower transistor electrode.

3. A transistor according to claim 1, in which said threshold dopant distribution has a first lateral peak value in said peak, said first lateral peak value having a magnitude such that said transistor has a design threshold voltage.

4. A transistor according to claim 2, in which said lateral peak value has a magnitude such that said transistor has a design threshold voltage.

5. A DRAM having an array of memory cells comprising a vertical transistor disposed above and connected to a capacitor, said vertical transistor extending downwardly from an upper transistor electrode toward a capacitor electrode and comprising:

a lower transistor electrode formed in a lower level of said transistor and connected to said capacitor;

a gate dielectric extending downwardly from said upper transistor electrode toward said lower transistor electrode and abutting a transistor body formed in said semiconductor substrate;

a threshold dopant distribution of dopant disposed in said semiconductor body, said dopant distribution having a peak adjacent said gate dielectric and a lower value of dopant concentration away from said gate dielectric; and

a transistor gate disposed adjacent said gate dielectric on a side opposite said transistor body.

6. A DRAM according to claim 5, in which said threshold dopant distribution has a first lateral peak value in an upper portion of said transistor body and a second lateral peak value lower than said first lateral peak value in a lower portion of said body, whereby said concentration value of said threshold dopant distribution in said channel has a minimum value near said lower transistor electrode.

7. A method of making an integrated circuit having a set of vertical transistors comprising the steps of:

forming a set of lower transistor electrodes adjacent to a set of apertures in a semiconductor substrate;

implanting a threshold ion distribution in a set of transistor bodies located above said set of lower transistor electrodes, said ion distribution having a peak located adjacent a vertical surface of said semiconductor substrate located above said set of lower transistor electrodes;

forming a set of upper transistor electrodes in said semiconductor substrate above said set of lower transistor electrodes;

forming a set of transistor gates, transistor bodies and gate dielectrics between said lower and upper transistor electrodes in said set of apertures, thereby forming a set of vertical transistors having channels in said semiconductor substrate between said upper and lower electrodes; and

completing said integrated circuit.

8. A method of making an integrated circuit having a set of vertical transistors according to claim 7, in which:

Said step of implanting a threshold ion distribution is preceded by a step of forming a blocking layer on a top surface of said semiconductor substrate; and

Said step of implanting a threshold ion distribution is performed at an angle with respect to the vertical, whereby ions pass through said set of apertures and penetrate said transistor bodies from the side.

9. A method of making an integrated circuit having a set of vertical transistors according to claim 8, in which:

Said step of implanting a threshold ion distribution is followed by a step of removing said blocking layer; and

A step of implanting a laterally uniform threshold ion distribution is performed vertically, whereby ions penetrate said transistor bodies from said substrate surface and form a laterally uniform body ion distribution.

10. A method of making an integrated circuit having a set of vertical transistors according to claim 8, in which:

Said step of implanting a threshold ion distribution is preceded by a step of implanting a lower ion distribution at an angle with respect to the vertical, said lower ion distribution having a lower dose magnitude that is less than a corresponding dose magnitude of said threshold ion distribution;

forming a set of temporary plugs within said set of apertures, whereby said threshold ion distribution, penetrates said transistor bodies from the side only in an upper portion of said set of transistor bodies located above said set of temporary plugs; and

Removing said set of temporary plugs.

11. A method according to claim 10, in which:

Said step of implanting a threshold ion distribution is followed by a step of removing said blocking layer; and

A step of implanting a laterally uniform threshold ion distribution is performed vertically, whereby ions penetrate said transistor bodies from said substrate surface and form a laterally uniform ion distribution.

12. A method of making an integrated circuit having a set of vertical transistors according to claim 7, in which:

Said step of implanting a threshold ion distribution is preceded by a step of forming a blocking layer on a top surface of said semiconductor substrate; and

Said step of forming a blocking layer on a top surface of said semiconductor substrate is followed by a step of forming a second set of apertures about said set of apertures and exposing a channel region of said semiconductor substrate; and

Said step of implanting said threshold ion distribution is performed vertically through said second set of apertures.

13. A method of making an integrated circuit having a set of vertical transistors according to claim 12, in which:

Said step of implanting a threshold ion distribution is followed by a step of removing said blocking layer; and

A step of implanting a laterally uniform threshold ion distribution is performed vertically, whereby ions penetrate said transistor bodies from said substrate surface and form a laterally uniform body ion distribution.