Method and system for proportional plus integral loop compensation using a hybrid of switched capacitor and linear amplifiers

• US 20030169107A1
• Filed: 10/17/2002
• Published: 09/11/2003
• Est. Priority Date: 10/19/2001
• Status: Abandoned Application

• Current Assignee: Clare Micronix Integrated Systems, Inc.
• Original Assignee: Clare Micronix Integrated Systems, Inc.
• Inventors: LeChevalier, Robert
• Application Number:
  US10/274,429
• Publication Number:
  US 20030169107A1
• Time in Patent Office: Days
• US Class Current: 330/124R
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0259 with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/029 by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
• CPC Class Codes: G09G 3/3216 using a passive matrix
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements

Abstract

A proportional plus integral compensation network employs a combination of linear components and switched capacitor components so as to reduce the physical size of the components required to implement the network. The compensation network comprises a linear, proportional amplifier, an integrator, in parallel with the amplifier, having a switched capacitor as a resistive element, and a summing element to combine the output signals of the amplifier and the integrator to provide a stable, amplified feedback signal.

Claims

1. A compensation network circuit comprising:

a linear amplifier having an input and an output;

an integrator in parallel with said linear amplifier, having an input and an output, wherein said integrator includes a switched capacitor which provides an effective resistance; and

a summing element connected to said output of said linear amplifier and said output of said integrator so as to provide a stable, amplified feedback signal.

2. The compensation network circuit of claim 1, wherein said linear amplifier comprises:

a first resistor having an output and receiving an input signal from a voltage source;

an operational amplifier having an inverting input connected to said output of said first resistor;

a second resistor connected in the feedback path of said operational amplifier; and

a reference voltage input connected to a non-inverting input of said operational amplifier.

3. The compensation network circuit of claim 1, wherein said switched capacitor comprises

a first switch receiving a first clock input and having an output;

a first capacitor having an input connected to said output of said first switch and an output connected to ground; and

a second switch having a second clock input and an input connected to said first capacitor, and an output.

4. The compensation network circuit of claim 3, wherein said first switch and said second switch are switching MOSFET'"'"'s.

5. The compensation network circuit of claim 3, wherein said integrator further comprises an operational amplifier having an inverting input connected to said output of said second switch, a non-inverting input connected to said reference voltage, and an output from said operational amplifier.

6. The compensation network circuit of claim 1, wherein said summing element is a passive resistor summing network.

7. The compensation network circuit of claim 1, wherein said summing element is an active amplifier.

8. The compensation network circuit of claim 1, implemented in a power conversion circuit.

9. The compensation network circuit of claim 1, implemented in a portable display device.

10. A compensation network circuit comprising:

an input voltage;

a proportional amplifier comprising;

a first impedance element receiving said input voltage, and an output connected to an inverting input of a first operational amplifier;

a reference voltage connected to a non-inverting input of said operational amplifier;

a second impedance element connected in the feedback path of said operational amplifier, and an output from said first operational amplifier;

an integrator comprising;

a first switch receiving said input voltage and a first clock signal, and having an output;

a first capacitor receiving said output of said first switch, and an output connected to ground;

a second switch connected to said first capacitor, receiving a second clock signal, and having an output;

a second operational amplifier having an inverting input from said output of said second switch, a non-inverting input receiving said reference voltage, a second capacitor in a feedback path of said second operational amplifier, and an output from said second operational amplifier; and

a summing element, having an input from said output of said first operational amplifier and said output of said second operational amplifier, and having an output so as to provide a stable, amplified feedback signal.

11. The circuit of claim 10, wherein said first switch and said second switch are switching MOSFET'"'"'s.

12. The circuit of claim 10, wherein said summing element comprises a first resistive element receiving an input from said output of said first operational amplifier and an output, and a second resistive element receiving an input from said output of said second operational amplifier and having an output connected to said output of said first resistive element of said summing network

13. A compensation network circuit comprising:

a voltage input;

a clock input;

a flip flop receiving said voltage input, and having a reset input, an output, and an inverted output;

a boost circuit connected to said output of said flip flop, and having a voltage output;

a linear amplifier receiving said voltage output, and having an output;

an integrator in parallel with said linear amplifier, receiving said voltage output, and having an output, and wherein said integrator includes a switched capacitor which provides an effective resistance;

a summing element connected to said output of said linear amplifier and said output of said integrator so as to provide a stable, amplified feedback signal; and

a switch control circuit receiving said stable, amplified feedback signal from said summing network and having an input and an output, wherein said output is connected to said reset input of said flip flop.

14. A method of loop compensation comprising:

proportionally amplifying an input with a linear amplifier;

integrating said input using at least one switched capacitor; and

summing said amplified input and said integrated input so as to produce a stable, amplified feedback signal.

15. The method of claim 14, wherein said summing is performed by a passive resistor summing network.

16. The method of claim 14, wherein said summing is performed by an active amplifier.

17. The method of claim 14, further comprising controlling a power converter circuit using said method of loop compensation.

18. The method of claim 14, wherein said method is performed in a portable display device.

19. A compensation network circuit comprising:

a signal input;

a first signal path having linear components and an output, and receiving said signal input;

a second signal path having at least one switched capacitor and an output, and receiving said signal input; and

a summing element receiving a signal from said output of said first path and an output of said second path so as to provide a stable, amplified output signal.

20. The circuit of claim 19, wherein said first signal path comprises a first resistor receiving said signal input, an operational amplifier having an input connected to an output of said first resistor and an input receiving a reference voltage, a second resistor in a feedback path of said operational amplifier, and an output connected to an output of said operational amplifier.

21. The circuit of claim 19, wherein said switched capacitor comprises:

a first switch receiving a first clock input and having an output;

a first capacitor having an input connected to said output of said first switch and an output connected to ground; and

a second switch having a second clock input and an input connected to said first capacitor, and an output.

22. The circuit of claim 21, wherein said first switch and said second switch are switching MOSFET'"'"'s.

23. The circuit of claim 19, wherein said second signal path comprises an integrator.

24. A compensation network circuit comprising:

means for proportionally amplifying a signal input with a linear amplifier;

means for integrating said signal input using at least one switched capacitor; and

means for summing said amplified signal and said integrated signal so as to provide a stable, amplified signal.

25. The circuit of claim 24, wherein said switched capacitor comprises:

a first switch receiving a first clock input and having an output;

a first capacitor having an input connected to said output of said first switch and an output connected to ground; and

a second switch having a second clock input and an input connected to said first capacitor, and an output.

26. The circuit of claim 25, wherein said first switch and said second switch are switching MOSFET'"'"'s.

27. The circuit of claim 24, wherein said summing is performed by a passive resistor summing network.

28. The circuit of claim 24, wherein said summing is performed by an active amplifier.

29. The circuit of claim 24, further comprising controlling a power converter circuit using said method of loop compensation.

30. The circuit of claim 24, wherein said method is performed in a portable display device.

31. A compensation network circuit, comprising:

a signal input;

a first signal path, receiving said signal input and having an output;

a second signal path, receiving said signal input and having an output, comprising;

an integrator, having an input and an output, wherein said integrator includes a switched capacitor which provides an effective resistance;

a transconductance amplifier, having an input coupled to said output of said integrator, and an output; and

a linear amplifier having an input coupled to said output of said first signal path and said output of said second signal path, and an output so as to provide a stable, amplified feedback signal.

32. The compensation circuit of claim 31, wherein said first signal path has an input from a voltage source and comprises a resistor having an output.

33. The compensation circuit of claim 31, wherein said linear amplifier comprises:

an operational amplifier having an inverting input connected to said first signal path and said output of said transconductance amplifier; and

a resistor connected in the feedback path of said operational amplifier.

34. The compensation circuit of claim 31, wherein said switched capacitor comprises

a first switch receiving a first clock input and having an output;

a first capacitor having an input connected to said output of said first switch and an output connected to ground; and

a second switch having a second clock input and an input connected to said first capacitor, and an output.

35. The compensation circuit of claim 34, wherein said first switch and said second switch are switching MOSFET'"'"'s.

36. The compensation circuit of claim 34, wherein said integrator further comprises an operational amplifier having an inverting input connected to said output of said second switch, a non-inverting input connected to said reference voltage, and an output from said operational amplifier.

37. The compensation circuit of claim 31, implemented in a power conversion circuit.

38. The compensation circuit of claim 31, implemented in a portable display device.