High-speed analog-to-digital converter using a unique gray code

• US 20030169195A1
• Filed: 03/07/2003
• Published: 09/11/2003
• Est. Priority Date: 03/08/2002
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Quellan, Inc. (Renesas Electronics Corporation)
• Inventors: Kim, Andrew Joo, Hietala, Vincent Mark
• Granted Patent: US 6,816,101 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: H03M 1/0687 using fault-tolerant coding, e.g. parity check, error correcting codes H03M1/069 takes precedence
• CPC Class Codes: H03M 1/0809 of bubble errors, i.e. irregularities in thermometer codes
• CPC Class Codes: H03M 1/361 having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
• CPC Class Codes: H03M 7/16 Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
• CPC Class Codes: H04B 14/02 characterised by the use of pulse modulation in radio transmission relays H04B7/17

Abstract

A method for high speed communications uses an inventive Q-Gray code. The Q-Gray code simplifies the hardware needed to convert analog Q-Gray code signals to digital signals. An analog-to-digital converter can use a plurality of comparators for receiving the multilevel signal and a plurality of decoder blocks coupled to comparators for decoding the multilevel signal. Each decoder block can include an equal number of inputs. Specifically, each decoder block can also include a parity detector with an equal number of inputs. Each decoder block can also employ a bank of identical parity detectors relative to another decoder block. Each comparator of the analog to digital converter can have an individually or externally adjustable (or both) threshold level.

Claims

1. An analog to digital converter comprising:

a plurality of comparators for receiving a multilevel signal generated according to a code for which the maximum number of bit-toggles incurred in a bit channel while sequentially traversing the code is minimized;

a plurality of decoder blocks coupled to comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of inputs, whereby the analog to digital converter has a simple design that reduces dissipated power and increases achievable operational speeds for communications.

2. The analog to digital converter of claim 1, wherein the comparators can process a multilevel signal comprising non-uniformly spaced decoding thresholds.

3. The analog to digital converter of claim 1, wherein the multilevel signal is decoded into bit channels for which the bit error rates are substantially evenly distributed.

4. The analog to digital converter of claim 1, wherein each decoder block comprises a parity detector with an equal number of inputs.

5. The analog to digital converter of claim 1, wherein each decoder block comprises a bank of identical parity detectors relative to another decoder block.

6. The analog to digital converter of claim 1, wherein each comparator has an individually adjustable threshold level.

7. The analog to digital converter of claim 1, wherein each comparator has an externally controllable threshold level.

8. An analog to digital converter comprising:

a plurality of comparators with adjustable thresholds for receiving a multilevel signal;

a plurality of decoder blocks coupled to the comparators for decoding the multilevel signal, wherein each decoder block comprises a plurality of identical parity detectors relative to another decoder block, whereby the analog to digital converter has a simple design that reduces dissipated power and increases communication speed.

9. The analog to digital converter of claim 8, wherein the multilevel signal is decoded into bit channels for which the bit error rates are substantially evenly distributed.

10. The analog to digital converter of claim 8, wherein the multilevel signal is decoded according to a code for which the maximum number of bit-toggles incurred in a bit channel while sequentially traversing the code is minimized.

11. The analog to digital converter of claim 8, wherein each decoder block comprises an equal number of inputs.

12. The analog to digital converter of claim 8, wherein each parity detector has an equal number of inputs.

13. The analog to digital converter of claim 8, wherein each comparator has an individually adjustable threshold level.

14. The analog to digital converter of claim 8, wherein each comparator has an externally controllable threshold level.

15. An analog to digital converter comprising:

a plurality of comparators for receiving a multilevel signal generated by a code for which the bit error rate is substantially evenly distributed across each bit channel when decoded;

a plurality of decoder blocks coupled to the comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of parity detectors, whereby the analog to digital converter reduces power consumption.

16. The analog to digital converter of claim 15, wherein the comparators can process a multilevel signal comprising non-uniformly spaced decoding thresholds.

17. The analog to digital converter of claim 15, wherein the multilevel signal is decoded according to a code for which the maximum number of bit-toggles incurred in a bit channel while sequentially traversing the code is minimized.

18. The analog to digital converter of claim 15, wherein each decoder block comprises an equal number of inputs.

19. The analog to digital converter of claim 15, wherein each parity detector has an equal number of inputs.

20. The analog to digital converter of claim 15, wherein each comparator has an individually adjustable threshold level.

21. The analog to digital converter of claim 15, wherein each comparator has an externally controllable threshold level.

22. An analog to digital converter comprising:

a plurality of comparators for receiving a multilevel signal, each comparator having an individually adjustable threshold level;

a plurality of decoder blocks coupled to the comparators for decoding the multilevel signal, wherein each decoder block comprises identical hardware relative to another decoder block, whereby the analog to digital converter has a simple design that increases communication speeds.

23. The analog to digital converter of claim 22, wherein the multilevel signal is decoded according to a code for which the maximum number of bit-toggles incurred in a bit channel while sequentially traversing the code is minimized.

24. The analog to digital converter of claim 22, wherein the comparators can process a multilevel signal comprising non-uniformly spaced decoding thresholds.

25. The analog to digital converter of claim 22, wherein the hardware comprises parity detectors.

26. The analog to digital converter of claim 25, wherein each parity detector has an equal number of inputs.

27. The analog to digital converter of claim 22, wherein each decoder block comprises an equal number of inputs.

28. The analog to digital converter of claim 22, wherein each comparator has an externally controllable threshold level.

29. The analog to digital converter of claim 22, wherein inputs are evenly distributed to each decoder block.

30. An analog to digital converter comprising:

a plurality of comparators for receiving a multilevel signal generated according to a three bit Gray code derived from a bit translation operating list comprising ABCBABC with an operator comprising B and the operator returning an original seed from a last word in the three bit Gray code;

a plurality of decoder blocks coupled to comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of inputs.

31. The analog to digital converter of claim 30, wherein the code producing the multilevel signal is further derived by cyclically rotating the bit translation operating list.

32. The analog to digital converter of claim 30, wherein the code producing the multilevel signal is further derived by interchanging bit channel assignments.

33. An analog to digital converter comprising:

a plurality of comparators for receiving a multilevel signal generated according to a four bit Gray code derived from a bit translation operating list comprising CBCADABCBADBDCD with an operator comprising A and the operator returning an original seed from a last word in the four bit Gray code;

a plurality of decoder blocks coupled to comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of inputs.

34. The analog to digital converter of claim 33, wherein the code producing the multilevel signal is further derived by cyclically rotating the bit translation operating list.

35. The analog to digital converter of claim 33, wherein the code producing the multilevel signal is further derived by interchanging bit channel assignments.

36. An analog to digital converter comprising:

a plurality of comparators for receiving a multilevel signal generated according to a five bit Gray code derived from a bit translation operating list comprising ABACABADABEBDCDEBEDCACDECEBDCDE, with an operator comprising D and the operator returning an original seed from a last word in the five bit Gray code;

a plurality of decoder blocks coupled to comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of inputs.

37. The analog to digital converter of claim 36, wherein the code producing the multilevel signal is further derived by cyclically rotating the bit translation operating list.

38. The analog to digital converter of claim 36, wherein the code producing the multilevel signal is further derived by interchanging bit channel assignments.

39. A method for high speed communications comprising:

receiving data;

modulating the data to produce a multilevel signal according to a three bit Gray code derived from a bit translation operating list comprising ABCBABC with an operator comprising B and the operator returning an original seed from a last word in the three bit Gray code;

receiving the multilevel signal; and

converting the multilevel signal to a set of binary signals with decoder blocks, wherein each decoder block comprises an equal number of inputs.

40. The method of claim 39, further comprising deriving the multilevel signal by cyclically rotating the bit translation operating list to yield an alternate code.

41. The method of claim 39, further comprising deriving the multilevel signal by interchanging bit channel assignments.

42. A method for high speed communications comprising:

receiving data;

modulating the data to produce a multilevel signal according to a four bit Gray code derived from a bit translation operating list comprising CBCADABCBADBDCD with an operator comprising A and the operator returning an original seed from a last word in the four bit Gray code;

receiving the multilevel signal; and

converting the multilevel analog signal to a set of binary signals with decoder blocks, wherein each decoder block comprises an equal number of inputs.

43. The method of claim 42, further comprising deriving the multilevel signal by cyclically rotating the bit translation operating list to yield an alternate code.

44. The method of claim 42, further comprising deriving the multilevel signal by interchanging bit channel assignments.

45. A method for high speed communications comprising:

receiving data;

modulating the data to produce a multilevel signal to produce a five bit Gray code derived from a bit translation operating list comprising ABACABADABEBDCDEBEDCACDECEBDCDE, with an operator comprising D and the operator returning an original seed from a last word in the five bit Gray code;

receiving the multilevel signal; and

converting the multilevel signal to a set of binary signals with decoder blocks, wherein each decoder block comprises an equal number of inputs.

46. The method of claim 45, further comprising deriving the multilevel signal by cyclically rotating the bit translation operating list to yield an alternate code.

47. The method of claim 45, further comprising deriving the multilevel signal by interchanging bit channel assignments.