System and method of optimizing graphics processing

• US 20030169269A1
• Filed: 03/11/2002
• Published: 09/11/2003
• Est. Priority Date: 03/11/2002
• Status: Active Grant

• Current Assignee: Sony Interactive Entertainment Inc. (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Sasaki, Nobuo, Yamazaki, Takeshi
• Granted Patent: US 6,919,896 B2
• Time in Patent Office: Days
• US Class Current: 345/581
• CPC Class Codes: G06F 2209/501 Performance criteria
• CPC Class Codes: G06F 9/5066 Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs mappping at compile time, see G06F8/451
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A method and system for optimizing the processing of graphics is disclosed. The system may comprise at least one geometry processor and at least one graphics processor. A communication channel permits communication between the geometry and graphics processors. A control processor may communicate with the geometry and graphics processor through the communications channel. A method of processing graphics data in a computer system is provided to determine whether the geometry and graphics processors are being efficiently utilized. If necessary, one or more of the geometry and graphics processors are selectively assigned or unassigned to improve the efficiency of the graphics processing circuitry in performing the graphics task.

Claims

1. A method of optimizing the processing of graphics comprising the steps of:

a) assigning a first number of geometry processors to a graphics task and a second number of graphics processors to a graphics task;

b) collecting performance data from the second number of graphics processors over a period of time;

c) analyzing the collected performance data with an algorithm;

d) changing at least one of the first number of geometry processors assigned to the particular computer graphics task and the second number of graphics processors assigned to a particular computer graphics task depending on the analyzed results of the collected performance data.

2. The method of claim 1, wherein said first number of geometry processors transform object data into vertex data of polygons, and said second number of graphics processors render said polygons into a buffer memory, said step of collecting performance data over a period of time further includes:

a) counting the number of polygons that are rendered; and

b) calculating the average size of the polygons that are rendered.

3. The method of claim 2, wherein rendered polygons include a plurality of pixels, said step of calculating the average size of the rendered polygons includes counting the number of pixels rendered and dividing by the number of polygons rendered.

4. The method of claim 3, wherein said step of analyzing the collected performance data includes:

a) finding the number of polygons below a low threshold number of polygons;

b) finding the average size below a high threshold average size; and

c) determining to either

i) decrease the first number of geometry processors assigned to graphics tasks, or

ii) increase the second number of graphics processors assigned to graphics tasks, or

iii) decrease the first number of geometry processors and increase the second number of graphics processors.

5. The method of claim 4, wherein changing the number of geometry processors and the number of graphics processors includes:

a) decreasing the first number of geometry processors, or

b) increasing the second number of graphics processors, or

c) decreasing the first number of geometry processors and increasing the second number of graphics processors.

6. The method of claim 3, wherein analyzing the collected performance data includes:

a) finding the number of polygons greater than a high threshold number of polygons;

b) finding the average size of the polygons to be less than a small threshold average size; and

c) determining to either

i) increase the first number of geometry processors, or

ii) decrease the second number of graphics processors, or

iii) increase the first number of geometry processors and decrease the second number of graphics processors.

7. The method of claim 6, wherein changing the first number of geometry processors and the second number of graphics processors includes:

a) increasing the first number of geometry processors, or

b) decreasing the second number of graphics processors, or

c) increasing the first number of geometry processors and decreasing the second number of graphics processors.

8. The method of claim 1, wherein the period of time comprises approximately 10,000 clock cycles.

9. The method of claim 1, wherein changing at least one of the first number of geometry processors assigned to a graphics task and the second number of graphics processors assigned to a graphics task includes:

a) calculating a new configuration for a first cross-bar channel from among any arbitrary configuration;

b) calculating a new configuration for a set of buffers from among any arbitrary configuration;

c) calculating a new configuration for a second cross-bar channel from among any arbitrary configuration;

d) reconfiguring the first cross-bar channel to the new configuration;

e) reconfiguring the set of buffers to a new configuration; and

f) reconfiguring the second cross-bar channel to the new configuration.

10. The method of claim 1, further comprising:

a) providing a set of buffers;

b) providing a first cross-bar channel connecting the first number of geometry processors to the set of buffers; and

c) providing a second cross-bar channel connecting the second number of graphics processors to the set of buffers.

11. The method of claim 10, wherein changing the first number of geometry processors assigned to a graphics task and the second number of graphics processors assigned to a graphics task includes:

a) selecting a new configuration for the first cross-bar channel, the set of buffers, and the second cross-bar channel from among a pre-determined set of configurations; and

b) configuring the first cross-bar channel, the set of buffers, and the second cross-bar channel to the selected pre-determined configuration.

12. A method of optimizing the processing of graphics comprising the steps of:

a) assigning a first number of geometry processors to a graphics task and a second number of graphics processors to a graphics task, said first number of geometry processors transferring object data into vertex data of polygons, said second number of graphics processors rendering said polygons into a buffer memory, said polygons comprising a plurality of pixels;

b) collecting performance data from the second number of graphics processors over a period of time;

c) analyzing the collected performance data with an algorithm; and

d) increasing the number of polygons and decreasing the average size of polygons generated by the first number of geometry processors by increasing the tessellation of the graphical objects to be rendered depending on the results of analyzing the collected performance data.

13. The method of claim 12, wherein said step of collecting performance data includes:

a) counting the number of polygons rendered and the number of pixels rendered;

b) calculating the average polygon size;

c) collecting the number of texture misses; and

d) collecting the number of DRAM Page Breaks.

14. The method of claim 12, wherein calculating the average size of the polygons that are rendered includes collecting the number of pixels rendered and dividing by the number of polygons rendered.

16. The method of claim 14, wherein collecting performance data includes collecting average polygon size.

18. The method of claim 16, wherein the step of analyzing the performance data includes checking if the average polygon size is smaller than a specified size.

19. The method of claim 16, wherein the step of analyzing the performance data includes checking if the average polygon size is smaller than the size of a pixel.

15. A method of optimizing the processing of graphics comprising the steps of:

a) assigning a first number of geometry processors to a graphics task and a second number of graphics processors to a graphics task, said first number of geometry processors transforming object data into vertex data of polygons, said second number of graphics processors rendering said polygons into a buffer memory, said polygons comprising a plurality of pixels;

b) collecting performance data from the second number of graphics processors over a period of time;

c) analyzing the collected performance data with an algorithm; and

d) decreasing the number of polygons and increasing the average size of polygons generated by the first number of geometry processors by decreasing the tessellation of surfaces of said polygons to be generated depending on the results of analyzing the collected performance data.

17. The method of claim 15, wherein the collecting of average polygon size includes:

a) counting the number of polygons rendered and a number of pixels rendered;

b) collecting the number of pixels rendered; and

c) dividing the number of polygons rendered by the number of pixels rendered.

20. A method of optimizing the processing of graphics comprising the steps of:

a) assigning a first number of geometry processors to a graphics task and a second number of graphics processors to a graphics task, said graphics task including creating polygons having a plurality of pixels;

b) collecting performance data from the second number of graphics processors over a period of time;

c) analyzing the collected performance data with an algorithm;

d) changing at least one of the first number of geometry processors assigned to the graphics task, the second number of graphics processors assigned to the graphics task, and the amount of tessellation applied to said polygons by the first number of geometry processors.

22. The method of claim 20, wherein said step of collecting performance data includes collecting the number of page breaks, the number of polygons, and the average polygon size.

21. A method of optimizing the processing of graphics comprising the steps of:

a) assigning a first number of geometry processors to a graphics task and a second number of graphics processors to graphics task, said graphics task including creating polygons;

b) collecting performance data from the second number of graphics processors over a period of time;

c) analyzing the collected performance data with an algorithm;

d) spatially sorting the polygons being processed by the first number of geometry processors before sending the polygon data to be rendered by the second number of graphics processors.

23. The method of claim 21, further comprising the step of determining the average polygon size by comparing the number of polygons rendered to the number of pixels rendered.

24. The method of claim 21, wherein said step of analyzing the collected performance data with an algorithm includes checking for:

a) a number of polygons over a specified number;

b) an average size less than a specified size; and

c) a number of DRAM page breaks over a specified number of DRAM page breaks.

25. A method of processing graphics data in a computer system having graphics processing circuitry, said method comprising:

a) utilizing at least one geometry processor to perform at least a portion of a graphics task;

b) utilizing at least one graphics processor to perform at least another portion of said graphics task;

c) determining whether said at least one geometry processor and said graphics processor are being efficiently utilized; and

d) if necessary, selectively assigning or unassigning one or more of said at least one geometry and graphics processors to improve the efficiency of the graphics processing circuitry in performing said graphics task.

26. The method of claim 25 wherein said step of utilizing at least one geometry processor to perform at least a portion of a graphics task comprises performing 3-D to 2-D conversion of an object into vertex data of polygons.

27. The method of claim 26 wherein said step of utilizing at least one graphics processor to perform at least another portion of said graphics task comprises rendering of said polygon vertex data into a buffer memory.

28. The method of claim 27 wherein said polygons comprise the plurality of pixels, said step of determining whether said at least one geometry processor and said at least one graphics processor are being efficiently utilized comprises:

a) calculating the number of polygons that are rendered; and

b) calculating the average size of the polygons that are rendered.

29. The method of claim 28 wherein said step of calculating the average size of the polygons that are rendered includes counting the number of pixels rendered and dividing by the number of polygons rendered.

30. The method of claim 29 further comprising providing a set of buffers having a configuration, providing a first cross-bar channel having a configuration connecting said plurality of geometry processors to said set of buffers, and providing a second cross-bar channel having a configuration connecting said plurality of graphics processors to said set of buffers.

31. The method of claim 30 wherein said step of selectively assigning or unassigning one or more of said geometry and graphics processors comprises:

a) calculating a new configuration for said first cross-bar channel;

b) calculating a new configuration for said set of buffers;

c) calculating a new configuration for said second cross-bar channel;

d) reconfiguring said first cross-bar channel to said new configuration;

e) reconfiguring said set of buffers to a new configuration; and

f) reconfiguring said second cross-bar channel to said new configuration.

32. A computer system having graphics processing circuitry for processing graphics data, said system comprising:

a) at least one geometry processor for at least partially performing at least a portion of a graphics task;

b) at least one graphics processor for at least partially performing at least another portion of said graphics task;

c) a communication channel permitting communication between said at least one geometry and graphics processors; and

d) a control processor communicating with said geometry and graphics processors through said communication channel, said control processor determining whether said at least one geometry and graphics processors are being efficiently utilized and, if necessary, selectively assigning or unassigning one or more of said at least one geometry and graphics processors to improve the efficiency of said graphics processing circuitry in performing said graphics task.

33. The computer system of claim 32 wherein said at least one geometry processor comprises a plurality of geometry processors, and said at least one graphics processor comprises a plurality of graphics processors.

34. The computer system of claim 33 wherein said plurality of geometry processors perform 3-D to 2-D conversion of an object into vertex data of polygons.

35. The computer system of claim 34 wherein said plurality of graphics processors render said polygons into a buffer memory, said polygons comprising a plurality of pixels.

36. The computer system of claim 35 wherein said communication channel includes:

a) a first channel having a cross-bar architecture;

b) at least one buffer memory connected to receive data from said plurality of geometry processors through said first channel; and

c) a second channel having a one-to-one cross-bar architecture arranged to permit communication between said plurality of graphics processors and said at least one buffer memory.

37. The computer system of claim 36 wherein said communication channel facilitates communication of performance data between said plurality of graphics processors and said control processor.