Method and apparatus for improved jitter tolerance

• US 20030170022A1
• Filed: 01/23/2003
• Published: 09/11/2003
• Est. Priority Date: 03/06/2002
• Status: Active Grant

• Current Assignee: Alcatel-Lucent SA (Nokia Corporation)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Josef Moeller, Lothar Benedict Erhard
• Granted Patent: US 8,639,127 B2
• Time in Patent Office: Days
• US Class Current: 398/27
• CPC Class Codes: H04B 10/671 for controlling the input optical signal

Abstract

We demonstrate a novel type of data receiver, which has superior performance compared to a standard receiver when an input signal is distorted by timing jitter. A method and apparatus for improved timing jitter tolerance includes sampling an input signal more than once within a bit slot of the input signal and determining, using logic circuitry, from a combination of at least a subset of the samples, a resulting logic state for an output signal.

Claims

1. A method for improving the jitter tolerance of a receiver in an optical transmission system, comprising:

receiving an input optical signal;

sampling said input signal more than once within its bit slot; and

determining, using logic circuitry, from a combination of at least a subset of said more than one samples, a resulting logic state for an output signal, wherein said output signal exhibits an improved bit error rate (BER).

2. The method of claim 1, wherein said sampling comprises:

applying said input signal to a decision circuit; and

sampling a resulting signal from said decision circuit more than once within its bit slot.

3. The method of claim 2, wherein said resulting signal from said decision circuit is sampled by a Demultiplexer.

4. The method of claim 1, wherein said sampling comprises:

splitting said input signal into more than one substantially identical versions; and

applying said more than one substantially identical versions of said input signal into respective decision circuits;

wherein each of said respective decision circuits have a phase offset with respect to each other, causing the sampling of said more than one substantially identical versions of said input signal at different times.

5. The method of claim 1, wherein said input signal is an optical pulse.

6. The method of claim 5, wherein said optical pulse is converted to an electrical signal by an optical/electrical (O/E) converter prior to said sampling.

7. The method of claim 5, wherein said optical pulse is a return-to-zero (RZ) optical pulse.

8. The method of claim 1, further comprising:

substantially eliminating any relative time delay between said more than one samples prior to said determining of a logic state.

9. The method of claim 8, wherein said input optical signal is a non-return-to-zero (NRZ) optical pulse.

10. The method of claim 1, wherein said logic circuitry comprises at least one logic device.

11. The method of claim 10, wherein said at least one logic device is an OR logic gate.

12. The method of claim 1, further comprising filtering said more than one samples prior to said determining of a logic state.

13. The method of claim 12, wherein each of said more than one samples are filtered relative to an associated delay between said more than one samples.

14. A receiver in an optical transmission system exhibiting an improved jitter tolerance, comprising:

a sampling circuit, for sampling an input signal more than once within a bit slot of said input signal; and

logic circuitry, for determining a resulting logic state of an output signal from a combination of at least a subset of said more than one samples, wherein said output signal exhibits an improved bit error rate (BER).

15. The receiver of claim 14, further comprising at least one delay device for substantially eliminating a relative time delay between said more than one samples prior to entering said logic device.

16. The method of claim 15, wherein said at least one delay device comprises at least one electrical delay line.

17. The receiver of claim 14, wherein said sampling circuit comprises:

at least one decision circuit, for determining a logic level of an input signal; and

a sampling device, for sampling the signal from said at least one decision circuit.

18. The receiver of claim 17, wherein said sampling device is a Demultiplexer.

19. The receiver of claim 18, wherein said Demultiplexer is selected from the group consisting of a 1:

2 Demultiplexer, a 1;

3 Demultiplexer, a 1;

4 Demultiplexer, and a 1;

5 Demultiplexer.

20. The receiver of claim 14, wherein said logic circuitry comprises at least one OR logic gate.

21. The receiver of claim 14, further comprising at least one filter for filtering said more than one samples prior to said determining of a logic state.