Methods and Apparatus for Optimizing Applications on Configurable Processors

• US 20030171907A1
• Filed: 03/04/2003
• Published: 09/11/2003
• Est. Priority Date: 03/06/2002
• Status: Abandoned Application

• Current Assignee: Improv Systems, Inc.
• Original Assignee: Improv Systems, Inc.
• Inventors: Novack, Steven, Gal-On, Shay
• Application Number:
  US10/248,939
• Publication Number:
  US 20030171907A1
• Time in Patent Office: Days
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 8/447 Target code generation

Abstract

The methods and apparatus of the present invention are directed to optimizing configurable processors to assist a designer in efficiently matching a design of an application and a design of a processor. In one aspect, methods and apparatus according to the present invention optimize a hardware architecture having one or more application specific processors. The methods and apparatus include modeling one or more of the application specific processors to generate a simulated hardware architecture and analyzing a compiled program for the simulated hardware architecture to determine one or more resource parameters for one or more program sections of the compiled program. The methods and apparatus provide one or more suggestions for modifying one or more of the application specific processors and the program sections in response to the resource parameter to optimize one or both of the compiled program and the hardware architecture.

Claims

1. An apparatus comprising a computer system for optimizing a hardware architecture having an application specific processor, the computer system comprising:

a simulator that models the application specific processor to generate a simulated hardware architecture; and

a profiler in communication with the simulator, the profiler analyzing a compiled program for the simulated hardware architecture to determine a resource parameter for a program section of the compiled program,

wherein the profiler provides a suggestion for modifying at least one of the application specific processor and the program section in response to the resource parameter to optimize at least one of the compiled program and the hardware architecture.

2. The apparatus of claim 1 wherein the resource parameter comprises a cost related to the hardware architecture.

3. The apparatus of claim 1 wherein the resource parameter comprises a power demand for the hardware architecture.

4. The apparatus of claim 1 wherein the resource parameter comprises a measure of performance of the compiled program.

5. The apparatus of claim 1 wherein the profiler that analyzes the compiled program analyzes the compiled program prior to execution of the compiled program on the simulated hardware architecture.

6. The apparatus of claim 1 wherein the profiler that analyzes the compiled program analyzes the compiled program during execution of the compiled program on the simulated hardware architecture.

7. The apparatus of claim 1 wherein the profiler that analyzes the compiled program analyzes the compiled program subsequent to execution of the compiled program on the simulated hardware architecture.

8. The apparatus of claim 1 wherein the profiler provides passive feedback to determine the resource parameter for at least one program section of the compiled program.

9. The apparatus of claim 1 wherein the profiler provides active feedback to determine the resource parameter for at least one program section of the compiled program.

10. The apparatus of claim 1 wherein the application specific processor is modified by configuring the application specific processor.

11. The apparatus of claim 1 wherein the resource parameter comprises a resource bottleneck.

12. The apparatus of claim 1 wherein the resource parameter comprises an available resource.

13. The apparatus of claim 1 wherein the profiler indicates a resource bottleneck.

14. The apparatus of claim 13 wherein the resource bottleneck is visually indicated.

15. The apparatus of claim 13 wherein the resource bottleneck is audibly indicated.

16. The apparatus of claim 1 wherein the compiled program comprises a very long instruction word program.

17. The apparatus of claim 1 wherein the suggestion for modifying the program section comprises reducing idleness in the program section.

18. The apparatus of claim 1 wherein the suggestion for modifying the program section comprises changing at least one instruction word in the program section.

19. The apparatus of claim 1 wherein the suggestion for modifying the program section comprises removing at least one instruction word in the program section.

20. The apparatus of claim 1 further comprising a graphical user interface that displays the resource parameter.

21. The apparatus of claim 1 further comprising a graphical user interface that displays the simulated hardware architecture.

22. The apparatus of claim 1 further comprising a compiler that generates the compiled program for the simulated hardware architecture.

23. The apparatus of claim 1 wherein the hardware architecture comprises at least one application specific processor.

24. The apparatus of claim 1 wherein the profiler analyzes the compiled program for the simulated hardware architecture to determine at least one resource parameter for at least one program section of the compiled program.

25. A method for optimizing a hardware architecture having an application specific processor, the method comprising:

modeling the application specific processor to generate a simulated hardware architecture;

analyzing a compiled program for the simulated hardware architecture to determine a resource parameter for a program section of the compiled program; and

providing a suggestion for modifying at least one of the application specific processor and the program section in response to the resource parameter to optimize at least one of the compiled program and the hardware architecture.

26. The method of claim 25 wherein the resource parameter comprises a cost associated with the hardware architecture.

27. The method of claim 25 wherein the resource parameter comprises a power requirement for the hardware architecture.

28. The method of claim 25 wherein the resource parameter comprises a measure of performance associated with the compiled program.

29. The method of claim 25 wherein the analyzing the compiled program to determine the resource parameter for the program section of the compiled program comprises analyzing the compiled program prior to executing the compiled program on the simulated hardware architecture.

30. The method of claim 25 wherein the analyzing the compiled program to determine the resource parameter for the program section of the compiled program comprises analyzing the compiled program during execution of the compiled program on the simulated hardware architecture.

31. The method of claim 25 wherein the analyzing the compiled program to determine the resource parameter for the program section of the compiled program comprises analyzing the compiled program subsequent to execution of the compiled program on the simulated hardware architecture.

32. The method of claim 25 wherein the analyzing the compiled program comprises providing passive feedback to determine the resource parameter for the program section of the compiled program.

33. The method of claim 25 wherein the analyzing the compiled program comprises providing active feedback to determine the resource parameter for the program section of the compiled program.

34. The method of claim 25 wherein the providing the suggestion for modifying the at least one of the application specific processor and the program section comprises providing at least one suggestion for modifying a configuration of the application specific processor.

35. The method of claim 25 wherein the resource parameter comprises a resource bottleneck.

36. The method of claim 25 wherein the resource parameter comprises an available resource.

37. The method of claim 25 wherein the analyzing the compiled program comprises indicating a resource bottleneck.

38. The method of claim 37 wherein the resource bottleneck is visually indicated.

39. The method of claim 37 wherein the resource bottleneck is audibly indicated.

40. The method of claim 25 wherein the compiled program comprises a very long instruction word program.

41. The method of claim 25 wherein the providing the suggestion for modifying the at least one of the application specific processor and the program section comprises providing a suggestion for reducing idleness in the program section.

42. The method of claim 25 wherein the providing the suggestion for modifying at least one of the application specific processor and the program section comprises providing a suggestion for modifying at least one instruction word in the program section.

43. The method of claim 25 wherein the providing the suggestion for modifying the at least one of the application specific processor and the program section comprises providing a suggestion for removing at least one instruction word in the program section.

44. The method of claim 25 wherein the hardware architecture comprises at least one application specific processor.

45. The method of claim 25 wherein the analyzing the compiled program comprises analyzing the compiled program to determine at least one resource parameter for at least one program section of the compiled program.

46. The method of claim 25 further including generating the compiled program for the simulated hardware architecture.

47. An apparatus for optimizing a hardware architecture including at least one application specific processor, the apparatus comprising:

means for modeling the at least one application specific processor to generate a simulated hardware architecture;

means for analyzing a compiled program for the simulated hardware architecture to determine a resource parameter for at least one program section of the compiled program; and

means for providing a suggestion for modifying at least one of the at least one application specific processor and the at least one program section in response to the resource parameter to optimize at least one of the compiled program and the hardware architecture.