Method and apparatus for clock synchronization between a system clock and a burst data clock

• US 20030172240A1
• Filed: 01/23/2001
• Published: 09/11/2003
• Est. Priority Date: 01/23/2001
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Johnson, Brian
• Granted Patent: US 6,751,717 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

The present invention coordinates the execution of commands, received in response to a continuous system clock, with the receipt of data in response to a burst clock. Command capture logic receives command information in response to the system clock. A storage element is responsive to the command capture logic for storing certain command information such as write commands. A two stage pipeline receives the command information from the storage element in response to the burst clock and outputs the command information in response to the system clock. Methods of operating the apparatus are also disclosed.

Claims

1. A circuit, comprising:

a storage element for storing information;

a first counter responsive to a first clock for controlling the reading of information out of said storage element;

a second counter responsive to a second clock and said first counter;

a first delay element responsive to said first counter and to information read out of said storage element; and

a second delay element responsive to said first delay element and said second counter.

2. The circuit of claim 1 wherein said first clock includes a burst data clock and said second clock includes a free running system clock.

3. The circuit of claim 2 wherein said information includes command and address information.

4. The circuit of claim 1 wherein said storage element includes a FIFO buffer and wherein said first and second delay elements include first and second latches, respectively.

5. A circuit, comprising:

a storage element for storing command information; and

a two stage pipeline for receiving command information from said storage element in response to a burst clock and for outputting said command information in response to a continuous clock.

6. The circuit of claim 5 wherein said storage element includes a storage element for storing command and address information, and wherein said two stage pipeline includes a two stage pipeline for receiving command and address information from said storage element and for outputting said command and address information.

7. The circuit of claim 5 wherein a first stage of said two stage pipeline includes a first counter responsive to said burst clock and a delay element responsive to said storage element and said first counter, and wherein a second stage of said two stage pipeline includes a second counter responsive to said continuous clock and said first counter, and a second delay element responsive to said first delay element and said second counter.

8. The circuit of claim 7 wherein said counters include double-edge clocked logic.

9. The circuit of claim 7 wherein said counters include counters that are enabled in response to a start signal.

10. An apparatus for coordinating the execution of commands with the receipt of data in a buffer in response to a burst clock, comprising:

command capture logic for receiving command information in response to a system clock;

a storage element responsive to said command capture logic for storing certain of said command information;

a first counter responsive to said burst clock for controlling the reading of command information out of said storage element;

a second counter responsive to said system clock and said first counter;

a first delay element responsive to said first counter and to said storage element; and

a second delay element responsive to said first delay element and said second counter for outputting said command information when data corresponding thereto is available.

11. The apparatus of claim 10 wherein said storage element includes a storage element for storing command and address information, and wherein said first counter is for controlling the reading of command and address information out of said storage element.

12. The apparatus of claim 10 wherein said counters include double-edge clocked logic.

13. The apparatus of claim 10 wherein said counters include counters that are enabled in response to a start signal.

14. An apparatus for coordinating the execution of commands with the receipt of data in a buffer in response to a burst clock, comprising:

command capture logic for receiving command information in response to a system clock;

a storage element responsive to said command capture logic for storing certain command information; and

a multi-stage pipeline for receiving command information from said storage element in response to said burst clock and for outputting said command information in response to said system clock.

15. The apparatus of claim 14 wherein said storage element includes a storage element for storing comma)n(d and address information, and wherein said multi-stage pipeline includes a two stage pipeline for receiving command and address information from said storage element and for outputting said command and address information.

16. The apparatus of claim 14 wherein a first stage of said multi-stage pipeline includes a first counter responsive to said burst clock and a delay element responsive to said storage element and said first counter, and wherein a second stage of said multi-stage pipeline includes a second counter responsive to said system clock and said first counter, and a second delay element responsive to said first delay element and said second counter.

17. The apparatus of claim 16 wherein said counters include double-edge clocked logic.

18. The apparatus of claim 16 wherein said counters include counters that are enabled in response to a start signal.

19. A memory device, comprising:

a plurality of memory cells;

an address decoder for receiving address information and for identifying at least one specific memory cell responsive to said address;

a buffer for receiving data for write operations in accordance with a burst clock;

a read/write circuit for reading data out of said specific cell or for writing said received data into said specific cell;

a control circuit for receiving command information and for generating control signals in response thereto for controlling said address decoder and said read/write circuit;

said memory device further comprising an apparatus for coordinating the execution of commands with the receipt of data in said buffer, comprising;

command capture logic for receiving and examining command information in response to a system clock, certain of said command information being passed onto said control circuit

a storage element responsive to said command capture logic for storing certain other of said command information;

a first counter responsive to said burst clock for controlling the reading of command information out of said storage element;

a second counter responsive to said system clock and said first counter;

a first delay element responsive to said first counter and to said storage element; and

a second delay element responsive to said first delay element and said second counter for outputting said command information to said control circuit when data corresponding thereto is available.

20. The memory device of claim 19 wherein said storage element includes a storage element for storing command and address information, and wherein said first counter is for controlling the reading of command and address information out of said storage element, and wherein said second delay element outputs said address information to said address decoder.

21. The memory device of claim 19 wherein said counters include double-edge clocked logic.

22. The memory device of claim 19 wherein said counters include counters that are enabled in response to a start signal.

23. A memory device, comprising:

a plurality of memory cells;

an address decoder for receiving address information and for identifying at least one specific memory cell responsive to said address;

a buffer for receiving data for write operations in accordance with a burst clock;

a read/write circuit for reading data out of said specific cell or for writing said received data into said specific cell;

a control circuit for receiving command information and for generating control signals in response thereto for controlling said address decoder and said read/write circuit;

said memory device further comprising an apparatus for coordinating the execution of commands with the receipt of data in said buffer, comprising;

command capture logic for receiving and examining command information in response to a system clock, certain of said command information being passed onto said control circuit

a storage element responsive to said command capture logic for storing certain other of said command information; and

a multi-stage pipeline for receiving command information from said storage element in response to said burst clock and for outputting said command information to said control logic in response to said system clock.

24. The memory device of claim 23 wherein said storage element includes a storage element for storing command and address information, and wherein said multistage pipeline includes a two stage pipeline for receiving command and address information from said storage element and for outputting said address information to said address decoder.

25. The memory device of claim 23 wherein a first stage of said multi-stage pipeline includes a first counter responsive to said burst clock and a delay element responsive to said storage element and said first counter, and wherein a second stage of said multi-stage pipeline includes a second counter responsive to said system clock and said first counter, and a second delay element responsive to said first delay element and said second counter.

26. The memory device of claim 25 wherein said counters include double-edge clocked logic.

27. The memory device of claim 25 wherein said counters include counters that are enabled in response to a start signal.

28. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus;

an output device coupled to the processor through the processor bus; and

a memory device coupled to the processor bus, said memory device comprising;

a plurality of memory cells;

an address decoder for receiving address information and for identifying at least one specific memory cell responsive to said address;

a buffer for receiving data for write operations in accordance with a burst clock;

a read/write circuit for reading data out of said specific cell or for writing said received data into said specific cell;

a control circuit for receiving command information and for generating control signals in response thereto for controlling said address decoder and said read/write circuit;

command capture logic for receiving and examining command information in response to a system clock, certain of said command information being passed onto said control circuit

a storage element responsive to said command capture logic for storing certain other of said command information;

a first counter responsive to said burst clock for controlling the reading of command information out of said storage element;

a second counter responsive to said system clock and said first counter;

a first delay element responsive to said first counter and to said storage element; and

a second delay element responsive to said first delay element and said second counter for outputting said command information to said control circuit when data corresponding thereto is available.

29. The computer system of claim 28 wherein said storage element includes a storage element for storing command and address information, and wherein said first counter is for controlling the reading of command and address information out of said storage element, and wherein said second delay element outputs said address information to said address decoder.

30. The computer system of claim 28 wherein said counters include double-edge clocked logic.

31. The computer system of claim 28 wherein said counters include counters that are enabled in response to a start signal.

32. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus,

an output device coupled to the processor through the processor bus; and

a memory device coupled to the processor bus, said memory device comprising;

a plurality of memory cells;

an address decoder for receiving address information and for identifying at least one specific memory cell responsive to said address;

a buffer for receiving data for write operations in accordance with a burst clock;

a read/write circuit for reading data out of said specific cell or for writing said received data into said specific cell;

a control circuit for receiving command information and for generating control signals in response thereto for controlling said address decoder and said read/write circuit;

command capture logic for receiving and examining comniand information in response to a system clock, certain of said command information being passed onto said control circuit

a storage element responsive to said command capture logic for storing certain other of said command information; and

a two stage pipeline for receiving command information from said storage element in response to said burst clock and for outputting said command information to said control logic in response to said system clock.

33. The computer system of claim 32 wherein said storage element includes a storage element for storing command and address information, and wherein said two stage pipeline includes a two stage pipeline for receiving command and address information from said storage element and for outputting said address information to said address decoder.

34. The computer system of claim 32 wherein a first stage of said two stage pipeline includes a first counter responsive to said burst clock and a delay element responsive to said storage element and said first counter, and wherein a second stage of said two stage pipeline includes a second counter responsive to said system clock and said first counter, and a second delay element responsive to said first delay element and said second counter.

35. The computer system of claim 34 wherein said counters include double-edge clocked logic.

36. The computer system of claim 34 wherein said counters include counters that are enabled in response to a start signal.

37. A method, comprising:

storing information;

transferring said stored information to a first device in response to a burst clock; and

transferring said information from said first device to a second device in response to a continuous clock.

38. The method of claim 37 wherein said step of storing information includes the step of storing command and address information and wherein said two transferring steps include transferring said command and address information.

39. A method, comprising:

storing information;

inputting said stored information into a pipeline in response to a burst clock; and

outputting said stored information from said pipeline in response to a continuous clock.

40. The method of claim 39 wherein said step of storing information includes the step of storing command and address information and wherein said inputting and outputting steps include inputting and outputting said command and address information.

41. A method, comprising:

storing information;

counting the clock pulses of a burst clock to produce a burst clock count;

transferring said stored information to a first device in response to said burst clock count;

counting the clock pulses of a continuous clock in response to said burst clock count to produce a continuous clock count; and

transferring said information from said first device to a second device in response to said continuous clock count.

42. The method of claim 41 wherein said step of storing information includes the step of storing command and address information and wherein said two transferring steps include transferring said command and address information.

43. The method of claim 41 wherein said step of counting the clock pulses of a burst clock includes counting both the rising and falling edges of said burst clock and wherein said step of counting the clock pulses of a continuous clock includes counting both the rising and falling edges of said continuous clock.

44. A method of coordinating the execution of commands with the receipt of data in response to a burst clock, comprising:

receiving command information in response to a continuous clock;

storing certain of said command information;

transferring said stored command information to a first device in response to said burst clock; and

transferring said command information from said first de %ice to a second device in response to said continuous clock.

45. The method of claim 44 wherein said step of storing information includes the step of storing command and address information and wherein said two transferring steps include transferring said command and address information.

46. A method of coordinating the execution of commands with the receipt of data in response to a burst clock;

comprising;

receiving command information in response to a continuous clock;

storing certain of said command information;

inputting said stored command information into a pipeline in response to a burst clock; and

outputting said stored command information from said pipeline in response to said continuous clock.

47. The method of claim 46 wherein said step of storing information includes the step of storing command and address information and wherein said inputting and outputting steps include inputting and outputting said command and address information.

48. A method of coordinating the execution of commands with the receipt of data in response to a burst clock;

comprising;

receiving command information in response to a continuous clock;

storing certain of said command information;

counting the clock pulses of said burst clock to produce a burst clock count;

transferring said stored command information to a first device in response to said burst clock count;

counting the clock pulses of said continuous clock in response to said burst clock count to produce a continuous clock count; and

transferring said command information from said first device to a second device in response to said continuous clock count.

49. The method of claim 48 wherein said step of storing information includes the step of storing command and address information and wherein said two transferring steps include transferring said command and address information.

50. The method of claim 48 wherein said step of counting the clock pulses of said burst clock includes counting both the rising and falling edges of said burst clock and wherein said step of counting the clock pulses of said continuous clock includes counting both the rising and falling edges of said continuous clock.

51. A method of processing a write command associated with an address and data, comprising:

receiving a write command and an address in response to a continuous clock;

receiving data in response to a burst clock; and

postponing the execution of said received write command until said data associated therewith is received, said write command being executed on said address in response to said continuous clock.