Communications system using rings architecture

• US 20030172257A1
• Filed: 07/02/2002
• Published: 09/11/2003
• Est. Priority Date: 07/02/2001
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Globespan Virata, Inc.
• Inventors: Greenblat, Ilia, Refaeli, Moshe
• Granted Patent: US 7,103,008 B2
• Time in Patent Office: Days
• US Class Current: 712/234
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04L 12/422 Synchronisation for ring networks Time Division Multiplex ring networks, e.g. SDH/SONET H04J3/085
• CPC Class Codes: H04L 12/427 with decentralised control
• CPC Class Codes: H04L 12/433 with asynchronous transmission, e.g. token ring, register insertion
• CPC Class Codes: H04L 12/437 Ring fault isolation or reconfiguration for SDH/SONET ring networks H04J3/085
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 12/4637 Interconnected ring systems
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5612 Ring
• CPC Class Codes: H04L 2012/5618 Bridges, gateways [GW] or interworking units [IWU]
• CPC Class Codes: H04L 2012/5627 Fault tolerance and recovery
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5656 using the AAL2
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 45/04 Interdomain routing, e.g. hierarchical routing
• CPC Class Codes: H04L 45/18 Loop-free operations
• CPC Class Codes: H04L 45/22 Alternate routing
• CPC Class Codes: H04L 45/302 Route determination based on requested QoS
• CPC Class Codes: H04L 45/306 : Route determination based on the nature of the carried application
• CPC Class Codes: H04L 45/50 : using label swapping, e.g. multi-protocol label switch [MPLS]
• CPC Class Codes: H04L 49/102 : using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/1553 : Interconnection of ATM switching modules, e.g. ATM switching fabrics
• CPC Class Codes: H04L 49/25 : Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/30 : Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3063 : Pipelined operation
• CPC Class Codes: H04L 49/3081 : ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/40 : Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 69/12 : Protocol engines
• CPC Class Codes: H04W 28/06 : Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365
• CPC Class Codes: H04W 40/00 : Communication routing or communication path finding
• CPC Class Codes: H04W 80/00 : Wireless network protocols or protocol adaptations to wireless operation
• CPC Class Codes: H04W 84/00 : Network topologies
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture. Additional inventive elements conveyed include: an architectural overview of a communications processor; a data path protocol support model for a communications processor; an exemplary network processor employed as the core packet processor for the communications processor; an exemplary rings-based SOC switch fabric architecture; and a variety of quality of support features.

Claims

1. A communications processor implemented as on at least one ring network, comprising:

a plurality of processors comprising ring members on the at least one ring network;

a plurality of DMA controllers on the at least one ring network, the DMA controllers controlling servicing of DMA requests by the plurality of processors;

a plurality of DMA agents coupled to the plurality of processors, each DMA agent being part of a ring member including a processor;

each DMA agent adapted to service processor DMA requests by determining whether a valid token exists from a pool of tokens reflecting available DMA controllers.

2. The communications processor of claim 1, wherein the tokens are DMA controller specific tokens issued by the DMA controllers to the DMA agents to indicate when specific DMA controller access is available.

3. The communications processor of claim 2, wherein each time a processor issues a DMA request the associated DMA agent determines whether a valid token exists and, if a valid token exists, services that DMA request using the DMA controller associated with that token.

4. The communications processor of claim 3, wherein the token is marked as used or invalid when the token is used to service a DMA request.

5. The communications processor of claim 3, wherein the associated DMA agent automatically requests a new valid token after an existing valid token is used to service the DMA request.

6. The communications processor of claim 1, wherein each DMA agent is adapted to request additional valid tokens when the number of valid tokens in the pool falls below a maximum number.

7. The communications processor of claim 1, wherein the pool of tokens is stored in a register written to by the DMA controllers.

8. The communications processor of claim 1, wherein the DMA agents service processor DMA requests by converting them to messages transmitted onto the at least one ring network.

9. The communications processor of claim 3, wherein if no valid token exists the DMA agent queues the DMA request until a valid token exists.

10. The communications processor of claim 1, wherein the DMA controllers distribute valid tokens by transmitting messages on the ring network that are received by specific DMA agents.

11. The communications processor of claim 1, wherein each DMA controller maintains a list of tokens including those tokens that have been distributed as valid tokens.

12. The communications processor of claim 1, wherein the DMA controllers responds to requests from the DMA agents for additional tokens with an invalid token when no valid tokens are available.

13. The communications processor of claim 1, wherein each DMA controller has a pool of up to 16 tokens for each DMA channel.

14. The communications processor of claim 1, wherein the DMA controllers are capable of reading registers having the pools of tokens for the DMA agents by issuing read messages traveling on the at least one ring network.

15. The communications processor of claim 1, wherein the processors comprise a plurality of network processors and the at least one ring network comprises a plurality of ring networks.