Circuit configuration and method for the switch-on/off control of a field-effect transistor

• US 20030173619A1
• Filed: 03/17/2003
• Published: 09/18/2003
• Est. Priority Date: 03/15/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Feldtkeller, Martin, Rieger, Walter, Friesacher, Wolfgang
• Granted Patent: US 6,858,895 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

A circuit configuration for the switch-on/off control of a DMOS power transistor has at least one first gate electrode and, separate from the latter, a second gate electrode, which are capacitively coupled to one another by a capacitance distributed over the field-effect transistor and which can be driven via separate external gate electrode terminals. The circuit configuration has two individual driver circuits and a generating circuit in order to feed a first drive signal to the first gate electrode and a second drive signal to the second gate electrode, the second drive signal being delayed with respect to the first drive signal.

Claims

1. A circuit configuration having a field-effect transistor, comprising:

a semiconductor body having a trench formed therein;

external gate terminals, including a first gate terminal and a second gate terminal;

at least one source electrode region formed in said semiconductor body;

at least one drain electrode region formed in said semiconductor body;

at least two gate electrodes, including a first gate electrode and a second gate electrode, formed vertically in said trench and in a manner insulated from one another and from said source electrode region and said drain electrode region, said first and second gate electrodes being capacitively coupled to one another by a capacitance distributed over the field-effect transistor, said gate electrodes each connected separately to one of said external gate terminals; and

a driver configuration connected to said external gate terminals and having driver circuits, including a first driver circuit and a second driver circuit, and a generating device, said driver configuration generating a first gate drive signal passed to said first gate terminal, and a second gate drive signal passed to said second gate terminal, said generating device generating the second gate drive signal in a delayed manner with respect to the first gate drive signal.

2. The circuit configuration according to claim 1, wherein said generating device has a delay element, and a delay time of the second gate drive signal is brought about by said delay element and is defined for a specific field-effect transistor type.

3. The circuit configuration according to claim 1, wherein said generating device has a delay element, and a delay time of the second gate drive signal is brought about by said delay element and is defined in such a way that a driving of said second gate electrode brought about by the second gate drive signal begins if an internal gate voltage of said first gate electrode has just reached its Miller plateau.

4. The circuit configuration according to claim 1, wherein in a case where the field-effect transistor is configured in such a way that said second gate electrode accepts at least part of a Miller capacitance from said first gate electrode, the circuit configuration further comprising:

a detection device for detecting a current which is induced, when the first gate drive signal is applied to said first gate terminal, in said second gate electrode with an opposite polarity with respect to a current flow in said first gate electrode, said generating device, driven by said detection device, generating the second gate drive signal directly in response to the current detected at said second gate electrode.

5. The circuit configuration according to claim 1, wherein said generating device generates the first and second gate drive signals with rectangular waveforms.

6. The circuit configuration according to claim 1, wherein said generating device generates the first gate drive signal with a staircase waveform and the second gate drive signal with a rectangular waveform.

7. The circuit configuration according to claim 1, further comprising a housing, said first and second driver circuits and said generating device are integrated in said housing together with the field-effect transistor.

8. The circuit configuration according to claim 1, wherein the field-effect transistor is a power field-effect transistor.

9. A method for operating a circuit configuration having a field-effect transistor with at least one source electrode region, at least one drain electrode region, and at least one first and second gate electrode, the first and second gate electrodes formed vertically in a trench of a semiconductor body and in a manner insulated from one another and from the source electrode region and the drain electrode region and are capacitively coupled to one another by a capacitance distributed over the field-effect transistor, the circuit configuration further having a driver configuration driving the field effect transistor, which comprises the steps of:

generating separately, via the driver configuration, a first driver signal and a second gate drive signal; and

applying the first and second gate drive signals to separate gate terminals in each case for the first and second gate electrodes, the second gate drive signal being generated in a delayed manner with respect to the first gate drive signal and being applied to the second gate terminal in a delayed manner.

10. The method according to claim 9, which further comprises defining a delay time by which the second gate drive signal is delayed with respect to the first gate drive signal and fed to the second gate terminal in each case in dependence on a field-effect transistor type.

11. The method according to claim 9, which further comprises defining a delay time by which the second gate drive signal is delayed with respect to the first gate drive signal and fed to the second gate terminal in such a way that control of the second gate electrode which is brought about by the second gate drive signal begins if an internal gate voltage of the first gate electrode has just reached its Miller plateau.

12. The method according to claim 9, wherein in a case where the second gate electrode accepts at least part of a Miller capacitance from the first gate electrode further performing the steps of:

detecting a current flow which flows, when the first gate drive signal is applied to the first gate terminal, in the second gate electrode with an opposite polarity with respect to a current flow in the first gate electrode; and

generating the second gate drive signal directly in response to the current flow detected at the second gate electrode.

13. The method according to claim 9, which further comprises generating the first and second gate drive signals with rectangular waveforms.

14. The method according to claim 9, which further comprises:

generating the first gate drive signal with a staircase waveform; and

generating the second gate drive signal with a rectangular waveform.

15. The method according to claim 9, which further comprises using a power field-effect transistor as the field-effect transistor.