High breakdown voltage low on-resistance lateral DMOS transistor

• US 20030173624A1
• Filed: 02/12/2003
• Published: 09/18/2003
• Est. Priority Date: 02/23/2002
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Inventors: Jeon, Chang-Ki, Choi, Yong-Cheol, Kim, Cheol-Joong
• Granted Patent: US 7,265,416 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type extends over the substrate. A body region of the first conductivity type is in the drift region. A source region of the second conductivity is in the body region. A gate extends over a surface portion of the body region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor. A drain region of the second conductivity type is in the drift region. The drain region is laterally spaced from the body region. A first buried layer of the second conductivity type is between the substrate and drift region. The first buried layer laterally extends from under the body region to under the drain region. A second buried layer of the first conductivity type is between the first buried layer and the drift region. The second buried layer laterally extends from under the body region to under the drain region.

Claims

1. A metal oxide semiconductor (MOS) transistor comprising:

a substrate of a first conductivity type;

a drift region of a second conductivity type over the substrate;

a body region of the first conductivity type in the drift region;

a source region of the second conductivity in the body region;

a gate extending over a surface portion of the body region, the surface portion of the body region extending between the source region and the drift region to form a channel region of the transistor;

a drain region of the second conductivity type in the drift region, the drain region being laterally spaced from the body region;

a first buried layer of the second conductivity type between the substrate and drift region, the first buried layer laterally extending from under the body region to under the drain region; and

a second buried layer of the first conductivity type between the first buried layer and the drift region, the second buried layer laterally extending from under the body region to under the drain region.

2. The MOS transistor of claim 1 further comprising an epitaxial layer of a second conductivity type over the substrate, the drift region being formed in the epitaxial layer.

3. The MOS transistor of claim 1 further comprising:

a body-contact region of the first conductivity type in the body region; and

a deep region of the first conductivity type vertically extending from under the source and body-contact regions through the drift region and terminating in the second buried layer.

4. The MOS transistor of claim 1 further comprising a field oxide between the body and drain regions, the gate extending over a portion of the field oxide.

5. The MOS transistor of claim 4 wherein the field oxide is adjacent the drain region but is laterally spaced from the body region.

6. The MOS transistor of claim 1 wherein the first buried layer forms a junction with each of the substrate, the drift region, and the second buried layer.

7. The MOS transistor of claim 1 wherein the second buried layer forms a junction with each of the first buried layer and the drift region.

8. The MOS transistor of claim 1 further comprising:

a drain electrode contacting the drain region;

a source electrode contacting the source region; and

an interlayer dielectric layer electrically isolating the gate, the source electrode, and the drain electrode from one another.

9. The MOS transistor of claim 1 wherein the first conductivity type is p-type and the second conductivity type is n-type.

10. The MOS transistor of claim 1 wherein the deep region and the body-contact region have a higher doping concentration than the body layer and the second buried layer.

11. The MOS transistor of claim 1 wherein the drain and source regions have a higher doping concentration than the drift region and the first buried layer.

12. A method of forming a metal oxide semiconductor (MOS) transistor, comprising:

providing a substrate of a first conductivity type;

forming a first buried layer of a second conductivity type in the substrate;

forming a second buried layer of the first conductivity type in the first buried layer;

forming an epitaxial layer of the second conductivity type over the substrate;

forming a drift region of a second conductivity type in the epitaxial layer;

forming a gate layer over the drift region;

forming a body region of the first conductivity type in the drift region such that the gate overlaps a surface portion of the body region;

forming a source region of the second conductivity in the body region; and

forming a drain region of the second conductivity type in the drift region, the drain region being laterally spaced from the body region;

wherein the first and second buried layers laterally extend from under the body region to under the drain region, and the surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor.

13. The method of claim 12 further comprising:

forming a body-contact region of the first conductivity type in the body region; and

forming a deep region of the first conductivity type vertically extending from under the source and body-contact regions through the drift region and terminating in the second buried layer.

14. The method of claim 12 further comprising forming a field oxide between the body and drain regions, the gate extending over a portion of the field oxide.

15. The method of claim 14 wherein the field oxide is formed adjacent the drain region but is laterally spaced from the body region.

16. The method of claim 12 wherein the first buried layer forms a junction with each of the substrate, the drift region, the epitaxial layer, and the second buried layer.

17. The method of claim 12 wherein the second buried layer forms a junction with each of the first buried layer and the drift region.

18. The method of claim 12 further comprising:

forming a drain electrode contacting the drain region;

forming a source electrode contacting the source region; and

forming an interlayer dielectric layer electrically isolating the gate, the source electrode, and the drain electrode from one another.

19. The method of claim 12 wherein the first conductivity type is p-type and the second conductivity type is n-type.

20. The method of claim 12 wherein the deep region and body-contact region have a higher doping concentration than the body layer and the second buried layer.

21. The method of claim 12 wherein the drain and source regions have a higher doping concentration than the drift region and the first buried layer.