Semiconductor apparatus

• US 20030173629A1
• Filed: 03/12/2003
• Published: 09/18/2003
• Est. Priority Date: 03/15/2002
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Gotoh, Masahito
• Granted Patent: US 6,781,154 B2
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

An object of the invention is to provide a semiconductor apparatus which simplifies a structure and reduces a possibility of occurrence of manufacture defect. Two of a first TFT and a second TFT which adjoins each other in a first direction are integrated in one semiconductor piece and share a source region electrically connected to a signal line and are formed in a symmetric shape in relation to a reference plane. Two scanning lines which extend in a second direction perpendicular to the first direction and are electrically connected to channel regions of the first and second TFTs and auxiliary capacitor electrodes for forming auxiliary capacitor between the auxiliary capacitor electrodes and drain electrodes electrically connected to the first and second TFTs are symmetrically arranged in relation to the reference plane.

Claims

1. A semiconductor apparatus comprising:

a plurality of signal lines extending in one direction and arranged substantially in parallel each other;

a plurality of scanning lines extending in the other direction intersecting in one direction and arranged substantially in parallel each other;

a plurality of driving electrodes arranged in the form of a matrix; and

switching elements having a source region electrically connected to the signal line, a channel region electrically connected to the scanning line and a drain region electrically connected to a driving electrode, for applying driving voltage from the drain region to the driving electrode by applying signal voltage from the signal line to the source region and from the scanning line to the channel region, the switching elements being formed so that every two of the plurality of switching elements which are adjoined in one direction are integrated in one semiconductor piece.

2. The semiconductor apparatus of claim 1, wherein the two switching elements share the source region.

3. The semiconductor apparatus of claim 1, wherein the two switching elements have a symmetrical shape in relation to the source region.

4. The semiconductor apparatus of claim 1, wherein the two scanning lines electrically connected to the two switching elements are symmetrically arranged in relation to the source region,

the drain electrodes for electrically connecting each of the driving electrodes to each of the drain regions of the two switching elements are symmetrically arranged in relation to the source region, and

auxiliary capacitor lines for forming each auxiliary capacitor between each of the auxiliary capacitor lines and each of the drain electrodes electrically connected to the two switching elements are symmetrically arranged in relation to the source region.

5. The semiconductor apparatus of claim 1, wherein at least a part of each of the channel regions of the two switching elements is located on a position opposite to the signal line in a direction perpendicular to one direction and perpendicular to the other direction.

6. A method of manufacturing a semiconductor apparatus comprising the steps of:

forming a semiconductor layer on a substrate and two drain regions on the semiconductor layer;

forming a gate insulating film on the substrate so as to cover the semiconductor layer;

forming scanning lines and auxiliary capacitor lines on the gate insulating film;

forming one source region between the two drain regions of the semiconductor layer and forming channel regions between the drain regions and the source region of the semiconductor layer;

forming a first interlayer insulating film on the gate insulating film so as to cover the scanning lines and the auxiliary capacitor lines and forming a signal line contact hole facing the source region and drain region contact holes each facing the drain region, the signal line contact hole and the drain region contact holes piercing both the gate insulating film and the first interlayer insulating film in a direction in which each insulating layer is stacked;

forming, on the first interlayer insulating film, a signal line which is connected to the source region via the signal line contact hole and forming drain electrodes each of which is connected to each of the drain regions of the semiconductor layer via each of the drain region contact holes;

forming a second interlayer insulating film on the first interlayer insulating film so as to cover the signal line and the drain electrodes and forming driving electrode contact holes each facing each of the drain electrodes, the each of the driving electrode contact holes piercing the second interlayer insulating film in the direction in which each insulating layer is stacked; and

forming, on the second interlayer insulating film, driving electrodes each of which is connected to each of the drain electrodes via each of the driving electrode contact holes.