Semiconductor device, method of manufacturing the same, and phase shift mask

• US 20030173675A1
• Filed: 01/24/2003
• Published: 09/18/2003
• Est. Priority Date: 03/15/2002
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Watanabe, Kenichi, Mitani, Junichi, Sawada, Toyoji, Hasegawa, Takumi, Kawano, Michiari, Sukegawa, Kazuo, Namba, Hiroshi
• Granted Patent: US 7,129,565 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: G03F 1/26 Phase shift masks [PSM]; PSM blanks; Preparation thereof
• CPC Class Codes: G03F 1/32 Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion,; Preparation thereof
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

Claims

1. A semiconductor device comprising:

an integrated circuit part in which an integrated circuit is formed;

a main wall part including metal films surrounding said integrated circuit part; and

a sub-wall part including metal films selectively formed between said integrated circuit part and said main wall part,

wherein said integrated circuit part, said main wall part and said sub-wall part share;

a semiconductor substrate; and

one or two or more interlayer insulation film(s) formed above said semiconductor substrate, in which openings are selectively formed, and

wherein a part of wires constituting said integrated circuit and a part of said metal films provided to each of said main wall part and said sub-wall part are substantially formed as a same layer.

2. The semiconductor device according to claim 1,

wherein said wires and said metal films provided to each of said main wall part and said sub-wall part are formed on said interlayer insulation films and in said openings.

3. The semiconductor device according to claim 2,

wherein said metal films provided to each of said main wall part and said sub-wall part are connected to one of said metal films underneath thereof or to said semiconductor substrate.

4. The semiconductor device according to claim 1, further comprising:

diffusion layers formed in regions where said metal films come in contact with said semiconductor substrate.

5. The semiconductor device according to claim 1,

wherein its plan shape is substantially a polygon, and

wherein said sub-wall part is arranged between a vertex of said polygon and said integrated circuit part.

6. The semiconductor device according to claim 1, further comprising:

a resistance value measuring part including;

a pair of electrodes arranged in a region between said sub-wall part and said integrated circuit part; and

pads for supplying signals from the outside to each of the pair of said electrodes.

7. The semiconductor device according to claim 1,

wherein lamination order of said interlayer insulation films and said metal films in said sub-wall part is the same as lamination order of said interlayer insulation films and said wires in said main wall part.

8. The semiconductor device according to claim 6,

wherein said resistance value measuring part includes interlayer insulation films and metal films whose lamination order is the same as lamination order of said interlayer insulation films and said metal films constituting said main wall part.

9. The semiconductor device according to claim 1,

wherein said sub-wall part constitutes a pair of electrodes, and

the semiconductor device further comprises pads for supplying signals from the outside to each of the pair of said electrodes.

10. The semiconductor device according to claim 1,

wherein widths of said metal films in said sub-wall part vary in two levels so that portions at the side of said semiconductor substrate are narrower, and said portions exist in said openings.

11. The semiconductor device according to claim 1,

wherein positions of said respective openings formed in said interlayer insulation films in said main wall part and said sub-wall part are the same in plan view.

12. The semiconductor device according to claim 1,

wherein a part of said sub-wall part is connected to said main wall part.

13. The semiconductor device according to claim 1,

wherein said sub-wall part includes a first wall piece which has a substantially fixed space from said main wall part in plan view.

14. The semiconductor device according to claim 13,

wherein said first wall piece is connected to said main wall part.

15. The semiconductor device according to claim 13,

wherein a plurality of said first wall pieces are arranged at regular intervals from said main wall part.

16. The semiconductor device according to claim 13,

wherein said sub-wall part includes a second wall piece which is formed between said first wall piece and said integrated circuit part and has a substantially fixed space from said first wall part.

17. The semiconductor device according to claim 16,

wherein the length of said second wall piece is smaller than the length of said first wall piece.

18. The semiconductor device according to claim 16,

wherein said first wall piece and said second wall piece are connected to each other.

19. The semiconductor device according to claim 16,

wherein said sub-wall part includes a third wall piece which is connected to said main wall part at two points and surrounds said first wall piece and said second wall piece with said main wall part and itself.

20. The semiconductor device according to claim 1,

wherein said sub-wall part includes a fourth wall piece which surrounds an arbitrary region between said integrated circuit part and said main wall part.

21. The semiconductor device according to claim 20,

wherein said sub-wall part includes a fifth wall piece surrounding said fourth wall piece.

22. The semiconductor device according to claim 21,

wherein said fourth wall piece and said fifth wall piece are connected to each other.

23. The semiconductor device according to claim 1,

wherein said sub-wall part includes a sixth wall piece which is connected to said main wall part at two points and surrounds an arbitrary region between said main wall part and said integrated circuit part with said main wall part and itself.

24. The semiconductor device according to claim 23,

wherein said sub-wall part includes a fourth wall piece which surrounds an arbitrary region between said integrated circuit part and said main wall part, and said fourth wall piece is surrounded by said main wall part and said sixth wall piece.

25. The semiconductor device according to claim 23,

wherein said sub-wall part includes a fifth wall piece surrounding said fourth wall piece, and said fifth wall piece is surrounded by said main wall part and the sixth wall piece.

26. A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, comprising the step of:

selectively forming a sub-wall part including metal films between said integrated circuit part and said main wall part, in parallel to formation of said integrated circuit part and said main wall part.

27. The method of manufacturing the semiconductor device according to claim 26,

wherein selectively forming said sub-wall part comprises the step of:

simultaneously forming a part of wires in said integrated circuit and a part of said metal films which is provided to each of said main wall part and said sub-wall part above a semiconductor substrate.

28. The method of manufacturing the semiconductor device according to claim 27,

wherein selectively forming said sub-wall part comprises the steps of:

forming interlayer insulation films above said semiconductor substrate over the entire surface; and

forming at least one opening in each of regions to be said integrated circuit part, said main wall part and said sub-wall part in said interlayer insulation films,

wherein said wires and said metal films are formed on said interlayer insulation films and in said openings.

29. The method of manufacturing the semiconductor device according to claim 26,

wherein a plan shape of the semiconductor device is substantially a polygon, and

wherein said sub-wall part is formed between a vertex of said polygon and said integrated circuit part.

30. The method of manufacturing the semiconductor device according to claim 26, further comprising the step of:

forming a resistance value measuring part including;

a pair of electrodes arranged in a region between said sub-wall part and said integrated circuit part; and

pads for supplying signals from the outside to each of the pair of said electrodes,

in parallel to formation of said integrated circuit part, said main wall part and said sub-wall part.

31. The method of manufacturing the semiconductor device according to claim 26,

wherein a part of said sub-wall part is connected to said main wall part.

32. A phase shift mask, comprising:

a phase shifter film formed on a transparent substrate; and

a light shield film formed in a scribe line region on said transparent substrate,

wherein a region surrounded by said scribe line region is constituted of an integrated circuit region with which an integrated circuit part is to be formed and a peripheral edge region with which a peripheral edge part in a periphery of said integrated circuit part is to be formed, and

wherein said light shield film is further formed at least in a part of said peripheral edge region and said integrated circuit region.

33. The phase shift mask according to claim 32,

wherein said peripheral edge region comprises a main wall part pattern for forming a main wall part surrounding said integrated circuit part.

34. The phase shift mask according to claim 33,

wherein said light shield film is formed only in a vicinity of said main wall part pattern in said peripheral edge region.

35. The phase shift mask according to claim 32,

wherein said peripheral edge region comprises a sub-wall part pattern for forming a sub-wall part formed between said integrated circuit part and said main wall part.

36. The phase shift mask according to claim 35,

wherein said light shield film is formed only in a vicinity of said main wall part pattern and said sub-wall part pattern in said peripheral edge region.

37. The phase shift mask according to claim 32,

wherein a contact hole pattern for forming a contact hole is formed in said phase shifter film in a region where said light shield film is not formed.

38. The phase shift mask according to claim 37,

wherein said contact hole pattern is a pattern for forming a contact hole reaching a source/drain region of a transistor.

39. The phase shift mask according to claim 32,

wherein a pattern formed in said phase shifter film in the region where said light shield film is formed is larger in size than a pattern formed in said phase shifter film in a region where said light shield film is not formed.

40. A phase shift mask, comprising:

a phase shifter film having an integrated circuit part pattern for forming an integrated circuit part, and a main wall part pattern for forming a main wall part which is formed to surround said integrated circuit part,

wherein an angle of a corner portion of said main wall part pattern is 100 degrees or larger.

41. A phase shift mask, comprising:

a phase shifter film having an integrated circuit part pattern for forming an integrated circuit part, a main wall part pattern for forming a main wall part which is formed to surround said integrated circuit part, and a sub-wall part pattern for forming a sub-wall part which is formed between said integrated circuit part and said main wall part,

wherein an angle of a corner portion of said sub-wall part pattern is 100 degrees or larger.

42. The phase shift mask according to claim 41,

wherein said main part pattern and said sub-wall part pattern are isolated from each other.

43. A phase shift mask, comprising:

a phase shifter film having an integrated circuit part pattern for forming an integrated circuit part, a main wall part pattern for forming a main wall part which is formed to surround said integrated circuit part, and a sub-wall part pattern for forming a sub-wall part which is formed between said integrated circuit part and said main wall part,

wherein said sub-wall part pattern is constituted of a plurality of linear wall part piece patterns.

44. A phase shift mask, comprising:

a phase shifter film having an integrated circuit part pattern for forming an integrated circuit part, a main wall part pattern for forming a main wall part which is formed to surround said integrated circuit part, and a sub-wall part pattern for forming a sub-wall part which is formed between said integrated circuit part and said main wall part,

wherein said sub-wall part pattern is constituted of a plurality of dot-shaped wall part piece patterns.