Input follower system and method

• US 20030174022A1
• Filed: 03/14/2003
• Published: 09/18/2003
• Est. Priority Date: 03/15/2002
• Status: Active Grant

• Current Assignee: Semtech Canada Corp. (Semtech Corporation)
• Original Assignee: Gennum Corporation
• Inventors: Webster, Stephen P., Zamir, Eliyahu D.
• Granted Patent: US 6,838,943 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 2370/047 using display data channel standard [DDC] communication
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H03F 2203/45458 the CSC comprising one or more capacitors
• CPC Class Codes: H03F 2203/45496 the CSC comprising one or more extra resistors
• CPC Class Codes: H03F 2203/45612 the IC comprising one or more input source followers as input stages in the IC
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/45197 Pl types H03F3/45224, H03F3/45251 take precedence
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/10 Compensating for variations in line balance

Abstract

An equalizer circuit for equalizing first and second differential input signals comprises a differential pair, a reactive load, and first and second input followers. The differential pair defines first and second input nodes and first and second output nodes, and the reactive load is coupled to the differential pair. The first input follower circuit is connected to the first input node of the differential pair and is operable to receive the first differential input signal and to receive a first feedback signal from the differential pair and in response to generate a first input signal at the first input node of the differential pair. The second input follower circuit is connected to the second input node of the differential pair and is operable to receive the second differential input signal and to receive a second feedback signal from the differential pair and in response to generate a second input signal at the second input node of the differential pair.

Claims

1. An equalizer circuit for equalizing first and second differential input signals, the equalizer circuit comprising:

a differential pair defining first and second input nodes and first and second output nodes;

a reactive load circuit coupled to the differential pair;

a first input follower circuit connected to the first input node of the differential pair, the first input follower circuit operable to receive the first differential input signal and to receive a first feedback signal from the differential pair and in response to generate a first input signal at the first input node of the differential pair; and

a second input follower circuit connected to the second input node of the differential pair, the second input follower circuit operable to receive the second differential input signal and to receive a second feedback signal from the differential pair and in response to generate a second input signal at the second input node of the differential pair;

wherein the first and second differential input signals are balanced DC signals, and the equalized first and second differential output signals are generated at the first and second output nodes, respectively.

2. The equalizer circuit of claim 1, wherein:

the first input follower circuit comprises a first operational amplifier configured to receive as input the first differential input signal and to receive the first feedback signal and provide unity feedback to generate the first input signal; and

the second input follower circuit comprises a second operational amplifier configured to receive as input the second differential input signal and to receive the second feedback signal and provide unity feedback to generate the second input signal.

3. The equalizer circuit of claim 2, wherein the differential pair comprises first and second field effect transistors.

4. The equalizer circuit of claim 3, wherein:

the source of the first field effect transistor is connected to an input node of the first operational amplifier to provide the first feedback signal; and

the source of the second field effect transistor is connected to an input node of the second operational amplifier to provide the second feedback signal.

5. The equalizer circuit of claim 4, wherein the reactive load circuit comprises a resistive and capacitive network.

6. The equalizer circuit of claim 5, further comprising current sinks interposed between the sources of the first and second field effect transistors and ground.

7. The equalizer circuit of claim 1, wherein the reactive load circuit comprises a resistive and capacitive network.

8. An equalizer circuit for equalizing first and second differential input signals, the equalizer circuit comprising:

a differential pair defining first and second gates, first and second drains, and first and second sources;

a reactive load circuit interposed between the first and second sources of the differential pair;

a first source follower circuit connected to the first gate and the first source; and

a second source follower circuit connected to the second gate and the second source.

wherein the first and second differential input signals are balanced DC signals and the equalized first and second differential output signals are generated at the first and second drains, respectively.

9. The equalizer circuit of claim 8, wherein:

the first source follower circuit defines a pair of input terminals and an output terminal, the output terminal coupled to the first gate and one of the input terminals coupled to the first source, the first source follower circuit configured to receive the first differential input signal at the other of the pair of input terminals and to generate a first input signal on the output terminal; and

the second source follower circuit defines a pair of input terminals and an output terminal, the output terminal coupled to the second gate and one of the input terminals coupled to the second source, the second source follower circuit configured to receive the second differential input signal at the other of the pair of input terminals and to generate a second input signal on the output terminal.

10. The equalizer circuit of claim 9, wherein the reactive load circuit comprises a resistive and capacitive network.

11. The equalizer circuit of claim 9, wherein the first and second source followers are configured to provide unity gain feedback from the first and second sources.

12. The equalizer circuit of claim 8, wherein the first and second source followers are configured to provide unity gain feedback from the first and second sources.

13. The equalizer circuit of claim 8, wherein the reactive load circuit comprises a resistive and capacitive network.

14. The equalizer circuit of claim 13, wherein the first and second source followers are configured as gyrators.

15. A method of equalizing first and second balanced DC differential signals, the method comprising:

providing feedback loops at the inputs to a differential pair, the differential pair defining first and second inputs and first and second outputs, the feedback loops independent of output signals generated by the differential pair at the first and second outputs;

generating first and second differential input signals from the first and second balanced DC differential signals and the feedback loop; and

applying the first and second differential input signals to the inputs of the differential pair.

16. The method of claim 15, wherein the step of providing feedback loops at the inputs to a differential pair comprise the step of providing unity gain feedback loops.

17. The method of claim 15, wherein the step of providing feedback loops at the inputs to a differential pair comprise the step of generating a feedback signal from a reactive load connected to the differential pair.

18. An equalizer circuit for equalizing first and second balanced DC differential signals, the equalizer circuit comprising:

means for providing feedback loops at the inputs to a differential pair, the means for providing feedback loops independent of the outputs of the differential pair;

means for generating first and second differential input signals from the first and second balanced DC differential signals and the feedback loop; and

means for applying the first and second differential input signals to the inputs of the differential pair.

19. The equalizer circuit of claim 18, wherein the means for providing feedback loops at the inputs to a differential pair is adapted for providing unity gain feedback loops.

20. The equalizer circuit of claim 18, wherein the means for providing feedback loops at the inputs to a differential pair is adapted for generating a feedback signal from a reactive load connected to the differential pair.

21. An equalizer circuit for equalizing first and second DC balanced differential input signals, the equalizer circuit comprising:

a differential pair defining first and second inputs and first and second outputs;

a reactive load circuit coupled to the differential pair; and

a pair of input follower circuits configured to receive the first and second DC balanced differential input signals and feedback signals from the reactive load and generate corresponding first and second input signals for the first and second inputs of the differential pair;

wherein the first and second equalized output signals are generated at the first and second output nodes, respectively.

22. The equalizer circuit of claim 21, wherein the differential pair comprises bipolar junction transistors.

23. The equalizer circuit of claim 21, wherein the pair of input follower circuits are further configured to provide unity gain.

24. The equalizer circuit of claim 23, wherein the input follower circuits comprise:

a first operational amplifier configured to receive as input the first DC balanced differential input signal and to receive a first feedback signal from the reactive load and generate the first input signal applied to the first input; and

a second operational amplifier configured to receive as input the second DC balanced differential input signal and to receive a second feedback signal from the reactive load and generate the second input signal applied to the second input.

25. The equalizer circuit of claim 24, wherein the differential pair comprises first and second field effect transistors.

26. The equalizer circuit of claim 25, wherein:

the source of the first field effect transistor is connected to an input node of the first operational amplifier to provide the first feedback signal; and

the source of the second field effect transistor is connected to an input node of the second operational amplifier to provide the second feedback signal.