Memory device which can change control by chip select signal

• US 20030174547A1
• Filed: 02/13/2003
• Published: 09/18/2003
• Est. Priority Date: 03/15/2002
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Higuchi, Yoshinobu, Nakata, Daisuke, Kitazaki, Kazuhiro, Wakasugi, Nobuyoshi
• Granted Patent: US 6,788,592 B2
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory device has an address terminal for inputting a plural bits of address signal, and a chip select terminal for inputting an external chip select signal, and an access mode controlling circuit which can switch a first control mode for controlling enable/disable of memory device according to plural external chip select signals and a predetermined address signal in the address signal to be input, and a second control mode for controlling the enable/disable according to a single external chip select signal. If the memory device is larger than a first memory area which can be controlled by a single chip select signal, the memory device can be directly connected to the memory control unit by setting the access mode control circuit to the first control mode. If the memory device is less than the first memory area, the access mode control circuit is set to the second control mode.

Claims

1. A memory device which is controlled to be in enable status and disable status by a chip select signal, comprising:

an address terminal for inputting a plural bits of address signal;

a chip select terminal for inputting an external chip select signal; and

an access mode control circuit which enables switching of a first control mode for executing enable/disable control of the memory device according to a plurality of external chip select signals and a predetermined address signal in said address signal to be input, and a second control mode for executing said enable/disable control of the memory device according to a single external chip select signal.

2. The memory device according to claim 1, wherein the access mode control circuit is set to said first control mode when memory area of said memory device is larger than memory area which a memory control unit for controlling said memory device can control using a single chip select signal.

3. The memory device according to claim 1, wherein the access mode control circuit is set to said second control mode when memory area of said memory device is equal to or smaller than memory area which the memory control unit for controlling said memory device can control using a single chip select signal.

4. The memory device according to claim 1, comprising a memory chip of which said access mode control circuit is set to said first control mode, and a package which has said plurality of external chip select terminals and accommodates said memory chip.

5. The memory device according to claim 1, comprising a memory chip of which said access mode control circuit is set to said second control mode, and a package which has said single external chip select terminal and accommodates said memory chip.

6. The memory device according to claim 1, wherein, in said first control mode, said access mode control circuit controls said memory device to be in enable status when one of the plurality of external chip select signals is in enable status, and controls said memory device to be in disable status according to said predetermined address signal, even if one external chip select signal is in enable status.

7. The memory device according to claim 4, wherein said memory chip further comprises a first most significant address terminal and a second most significant address terminal, a most significant address signal of said address signal to be input is supplied to said first most significant address terminal, said second most significant address terminal is fixed to a predetermined logical level, and said first control mode is executed according to said plurality of external chip enable signals and the input most significant address signal to be supplied to said first most significant address terminal.

8. The memory device according to claim 5, wherein said memory chip further comprises a first most significant address terminal and a second most significant address terminal, said first most significant address terminal is fixed to a predetermined logical level, the most significant address signal of said address signal to be input is supplied to said second most significant address terminal, and second control mode is executed.

9. A memory device which is controlled to be in enable status and disable status by a chip select signal, comprising:

an address terminal for inputting a plural bits of address signal;

a chip select terminal for inputting a plurality of external chip select signals; and

an access mode control circuit which executes enable/disable control of the memory device according to the plurality of external chip select signals and a predetermined address signal in said address signal to be input,

wherein said access mode control circuit controls said memory device to be in enable status when one of said plurality of external chip select signals is in enable status, and controls said memory device to disable status according to said predetermined address signal, even if one external chip select signal is in enable status.

10. The memory device according to claim 9, further comprising a higher internal address signal in addition to said plurality of bits of address signal to be input, wherein said access mode control circuit, when controlling in enable status, controls said internal address signal to be a predetermined logical level according to said address signal to be input.

11. A memory device which is controlled to be in enable status and disable status by a chip select signal, comprising:

an address terminal for inputting a plural bits of address signal;

a chip select terminal for inputting an external chip select signal; and

an access mode control circuit which enables switching of a first control mode for executing enable/disable control of the memory device according to a plurality of external chip select signals, and a second control mode for executing said enable/disable control of the memory device according to a single external chip select signal.

12. The memory device according to claim 11, comprising a memory chip of which said access mode control circuit is set to said first control mode, and a package which has said plurality of external chip select terminals and accommodates said memory chip.

13. The memory device according to claim 11, comprising a memory chip of which said access mode control circuit is set to said second control mode, and a package which has said single external chip select terminal and accommodates said memory chip.

14. A memory device which is controlled to be in enable status and disable status by a chip select signal, comprising:

an address terminal for inputting a plural bits of first address signal;

a chip select terminal for inputting a plurality of external chip select signals;

an access mode control circuit which executes said enable/disable control of the memory device according to the plurality of external chip select signals and a predetermined address signal of said first address signal to be input, and generates a second address signal;

an address buffer to which said first address signal and second address signal are supplied respectively and which generates non-inverted signals and inverted signals of said first and second address signals; and

a decoder for inputting and decoding the non-inverted signals and inverted signals of said address buffer,

wherein at least a part of said address buffer controls all said non-inverted signals and inverted signals to an activation level in response to an all select signal, regardless said first or second address signal to be supplied.

15. The memory device according to claim 14, further comprising a test mode detection circuit which detects a predetermined test mode and generates said all select signal.