Semiconductor memory device

• US 20030174573A1
• Filed: 01/14/2003
• Published: 09/18/2003
• Est. Priority Date: 03/13/2002
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Hideaki, Nakajima, Masao
• Granted Patent: US 6,894,943 B2
• Time in Patent Office: Days
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/2293 Timing circuits or methods
• CPC Class Codes: G11C 2207/065 Sense amplifier drivers
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device includes a memory bank which is divided into a plurality of memory blocks including a first memory block and a second memory block. A first sense amplifier control unit activates sense amplifiers connected with the first memory block, in response to a first activation signal. A second sense amplifier control unit activates sense amplifiers connected with the second memory block, in response to a second activation signal. A signal control unit outputs the first activation signal and the second activation signal to the first sense amplifier control unit and the second sense amplifier control unit, separately from each other, the signal control unit outputting the second activation signal to the second sense amplifier control unit by delaying the first activation signal by a predetermined time after the outputting of the first activation signal.

Claims

1. A semiconductor memory device comprising:

a memory bank which is divided into a plurality of memory blocks including a first memory block and a second memory block;

a first sense amplifier control unit activating sense amplifiers connected with the first memory block in the memory bank, in response to a first activation signal;

a second sense amplifier control unit activating sense amplifiers connected with the second memory block in the memory bank, in response to a second activation signal; and

a signal control unit outputting the first activation signal and the second activation signal to the first sense amplifier control unit and the second sense amplifier control unit, separately from each other, the signal control unit outputting the second activation signal to the second sense amplifier control unit by delaying the first activation signal by a predetermined time after the outputting of the first activation signal.

2. The semiconductor memory device of claim 1 wherein the memory bank comprises a dummy cell block provided between the first memory block and the second memory block, the dummy cell block being connected to a dummy bit line which is grounded at one end, so that the dummy cell block serves to absorb noise caused when one of the first and second memory blocks is activated and the other of the first and second memory blocks is deactivated.

3. The semiconductor memory device of claim 1 wherein memory cells of the first memory block and memory cells of the second memory block are connected to a common word line.

4. The semiconductor memory device of claim 1 wherein the signal control unit includes a plurality of logical elements that are connected in series, the plurality of logical elements including an input logical element receiving the first activation signal, and an arbitrarily selected one of the plurality of logical elements outputting the delayed first activation signal as the second activation signal, so that the predetermined time is adjustable.

5. The semiconductor memory device of claim 2 wherein the dummy bit line serves as a well tap in the middle of the semiconductor memory device where a potential change of a well of the semiconductor memory device may occur.

6. The semiconductor memory device of claim 1 wherein the semiconductor memory device is a nonvolatile memory device using a ferroelectric capacitor as a memory element.

7. A semiconductor memory device comprising:

a memory bank which is divided into a plurality of memory blocks including a first memory block and a second memory block;

a first sense amplifier control unit activating sense amplifiers connected with the first memory block in the memory bank, in response to a first activation signal;

a second sense amplifier control unit activating sense amplifiers connected with the second memory block in the memory bank, in response to a second activation signal;

a signal control unit outputting the first activation signal and the second activation signal to the first sense amplifier control unit and the second sense amplifier control unit, separately from each other, the signal control unit outputting the second activation signal to the second sense amplifier control unit by delaying the first activation signal by a predetermined time after the outputting of the first activation signal; and

a block select signal generating unit generating a first block select signal and a second block select signal based on an address signal that is supplied to the memory bank, the block select signal generating unit supplying the first block select signal and the second block select signal to the first sense amplifier control unit and the second sense amplifier control unit respectively.

8. The semiconductor memory device of claim 7 wherein the block select signal generating unit includes a pre-decoder, a first block select decoder, and a second block select decoder, the pre-decoder decoding the address signal, the first block select decoder decoding an output signal of the pre-decoder to output the first block select signal, and the second block select decoder decoding the output signal of the pre-decoder to output the second block select signal.

9. The semiconductor memory device of claim 7 wherein memory cells of the first memory block and memory cells of the second memory block are connected to a common word line.

10. The semiconductor memory device of claim 7 wherein the signal control unit includes a plurality of logical elements that are connected in series, the plurality of logical elements including an input logical element receiving the first activation signal, and an arbitrarily selected one of the plurality of logical elements outputting the delayed first activation signal as the second activation signal, so that the predetermined time is adjustable.

11. A semiconductor memory device comprising:

a memory bank which is divided into a plurality of memory blocks including a first memory block and a second memory block;

a first sense amplifier control unit activating sense amplifiers connected with the first memory block in the memory bank, in response to a first activation signal;

a second sense amplifier control unit activating sense amplifiers connected with the second memory block in the memory bank, in response to a second activation signal;

a signal control unit outputting the first activation signal and the second activation signal to the first sense amplifier control unit and the second sense amplifier control unit, separately from each other, the signal control unit outputting the second activation signal to the second sense amplifier control unit by delaying the first activation signal by a predetermined time after the outputting of the first activation signal; and

a dummy cell block provided between the first memory block and the second memory block, the dummy cell block being connected to a dummy bit line which is grounded at one end, so that the dummy cell block serves to absorb noise caused when one of the first and second memory blocks is activated and the other of the first and second memory blocks is deactivated,

wherein the signal control unit includes a timing control unit generating the second activation signal based on a logic level of a signal supplied from the dummy bit line of the dummy cell block.

12. The semiconductor memory device of claim 11, wherein the timing control unit includes a level adjustment circuit having a plurality of n-channel transistors connected in series, each configured to have a diode connection to the dummy bit line, an input transistor of the plurality of n-channel transistors being connected to the dummy bit line of the dummy cell block, an output transistor of the plurality of n-channel transistors being grounded.

13. The semiconductor memory device of claim 11 wherein memory cells of the first memory block and memory cells of the second memory block are connected to a common word line.