Self calibrating receive path correction system in a receiver

• US 20030174641A1
• Filed: 03/12/2002
• Published: 09/18/2003
• Est. Priority Date: 03/12/2002
• Status: Active Grant

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Rahman, Mahibur
• Granted Patent: US 7,130,359 B2
• Time in Patent Office: Days
• US Class Current: 370/206
• CPC Class Codes: H03D 3/008 Compensating DC offsets
• CPC Class Codes: H03D 3/009 Compensating quadrature phase or amplitude imbalances
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

A receiver (50) includes a self-calibrating receive path correction system for correction of I/Q gain and phase imbalances in a radio frequency signal. The system includes a signal-processing block (53), an I/Q phase imbalance detection and correction circuit (98), an I/Q gain imbalance detection and correction circuit (96), and an adaptive loop bandwidth control circuit (102). The I/Q phase imbalance detection and correction circuit (98) equalizes for the relative phase imbalance and the I/Q gain imbalance detection and correction circuit (96) equalizes for the relative gain imbalance between the I and Q channels created by the analog portion of a quadrature receiver. The adaptive loop bandwidth control circuit (102) dynamically adjusts at least one loop bandwidth for the I/Q gain imbalance detection and correction circuit (96) and the I/Q phase imbalance detection and correction circuit (98) on a slot boundary.

Claims

1. A receiver for receiving a radio frequency signal, the receiver having a self-calibrating receive path correction system for correction of an I/Q gain imbalance and an I/Q phase imbalance in the radio frequency signal, the receiver comprising:

a signal-processing block for processing the received radio frequency signal, thereby producing an unequalized I-signal and an unequalized Q-signal;

an I/Q phase imbalance detection and correction circuit coupled to the signal-processing block for equalizing a phase of the unequalized I-signal and a phase of the unequalized Q-signal, thereby producing a phase equalized I-signal and a phase equalized Q-signal;

an I/Q gain imbalance detection and correction circuit coupled to the I/Q phase imbalance detection and correction circuit for equalizing a gain of the phase equalized I-signal and a gain of the phase equalized Q-signal, thereby producing an I-image signal and a Q-image signal; and

an adaptive loop bandwidth control circuit coupled to the I/Q phase imbalance detection and correction circuit and to the I/Q gain imbalance detection and correction circuit for dynamically adjusting at least one loop bandwidth for the I/Q gain imbalance detection and correction circuit and the I/Q phase imbalance detection and correction circuit on at least one slot boundary.

2. A receiver as recited in claim 1 wherein the I/Q gain imbalance detection and correction circuit and the I/Q phase imbalance detection and correction circuit each use a SLOT_END control signal to detect the specified imbalances over a slot period, wherein the correction values are applied at the start of the next slot period.

3. A receiver as recited in claim 1 further comprising:

an image reject mixer circuit coupled to an output of the I/Q gain imbalance detection and correction circuit for downmixing the I-image signal and the Q-image signal, thereby producing a down-mixed I signal and a down-mixed Q-signal.

4. A receiver as recited in claim 1 comprising a zero intermediate frequency topology at baseband.

5. A receiver as recited in claim 1 comprising a very low intermediate frequency topology at baseband.

6. A receiver as recited in claim 1 wherein the signal-processing block includes digital offset correction during the processing of the received radio frequency signal, and further wherein an at least one PN training signal is used for a self-calibration of the I/Q phase imbalance detection and correction circuit and the I/Q gain imbalance detection and correction circuit during a warm-up sequence to compensate for imbalances due to the signal-processing block.

7. A receiver as recited in claim 1 wherein the signal-processing block comprises:

a local oscillator;

an I-quadrature mixer coupled to the local oscillator for down converting the radio frequency signal, thereby producing an I-signal component;

an I-channel anti-aliasing filter coupled to the I-quadrature mixer for attenuating out of band frequencies of the I-signal component, thereby producing an I-channel filtered signal;

an I-channel analog to digital converter coupled to the I-channel anti-aliasing filter for converting the I-channel filtered signal from an analog format to a digital format, thereby producing an I-channel digital signal;

an I-channel digital offset correction circuit coupled to the I-channel analog to digital converter for correcting for DC offsets of the I-channel digital signal created at the input to the I-channel anti-aliasing filter, thereby producing the unequalized I-signal;

an I-channel feedback path coupled between an output of the I-channel digital offset correction circuit and an input to the I-channel anti-aliasing filter to correct for the analog offsets at the input to the I-channel anti-aliasing filter, wherein the I-channel feedback path includes an I-channel digital PN training signal;

a Q-quadrature mixer coupled to the local oscillator for down converting the radio frequency signal, thereby producing a Q-signal component;

a Q-channel anti-aliasing filter coupled to the Q-quadrature mixer for attenuating out of band frequencies of the Q-signal component, thereby producing a Q-channel filtered signal;

a Q-channel analog to digital converter coupled to the Q-channel anti-aliasing filter for converting the Q-channel filtered signal from an analog format to a digital format, thereby producing a Q-channel digital signal;

a Q-channel digital offset correction circuit coupled to the Q-channel analog to digital converter for correcting for DC offsets of the Q-channel digital signal created at the input to the Q-channel anti-aliasing filter, thereby producing the unequalized Q-signal; and

a Q-channel feedback path coupled between an output of the Q-channel digital offset correction circuit and an input to the Q-channel anti-aliasing filter to correct for the analog offsets at the input to the Q-channel anti-aliasing filter, wherein the Q-channel feedback path includes a Q-channel digital PN training signal.

10. A receiver as recited in claim 1 wherein the I/Q gain imbalance detection and correction circuit comprises:

an I/Q gain correction feedback loop; and

a phase equalized feed forward signal path coupled to the I/Q gain correction feedback loop, wherein the I/Q gain correction feedback loop acquires an I/Q gain correction over a slot period, and further wherein the acquired I/Q gain correction is applied to the phase equalized feed forward signal path at the end of the slot period.

11. A receiver as recited in claim 10 wherein the I/Q gain correction feedback loop comprises:

a gain equalization subtractor for calculating a difference between an absolute value I-signal and an absolute value Q-signal, and

a gain equalization leaky integrator coupled to the gain equalization subtractor for averaging the difference, thereby producing an averaged magnitude error, wherein the averaged magnitude error is used to adjust a gain of the phase equalized feed forward signal path.

12. A receiver as recited in claim 11 wherein the averaged magnitude error is applied to a phase equalized Q-signal of the phase equalized feed forward signal path when the averaged magnitude error is less than unity.

13. A receiver as recited in claim 11 wherein the reciprocal of the average magnitude error is applied to a phase equalized I-signal of the phase equalized feed forward signal path when the averaged magnitude error is greater than unity.

8. A receiver as recited in claim I wherein the I/Q phase imbalance detection and correction circuit comprises:

an I/Q phase imbalance correction loop; and

a feed forward signal path coupled to the I/Q phase imbalance correction loop, wherein the I/Q phase imbalance correction loop acquires an I/Q phase imbalance over a slot period, and further wherein the I/Q phase imbalance acquired is applied at the end of the slot period.

9. A receiver as recited in claim 8 wherein the I/Q phase imbalance correction loop comprises:

a first multiplier for cross-multiplying the unequalized I-signal and the unequalized Q-signal,

a leaky integrator coupled to the first multiplier for averaging an output of the first multiplier to generate an accumulated phase error,

a second multiplier coupled to the output of the leaky integrator for multiplying the accumulated phase error by the unequalized I-signal, yielding a multiplier result, and

a subtractor coupled to the second multiplier for subtracting the multiplier result from the unequalized Q-signal thereby rotating the unequalized Q-signal in a phasor plane in a direction such that the accumulated phase error adaptively reaches a minimal steady state error.

14. Within a receiver including an I/Q phase imbalance detection and correction circuit and an I/Q gain imbalance detection and correction circuit, a method for correction of an I/Q gain imbalance and an I/Q phase imbalance in a received radio frequency signal using a self-calibrating receive path correction system, the method comprising:

performing a warm-up sequence of the receiver; and

adaptively controlling at least one loop band width of the I/Q phase imbalance detection and correction circuit and the I/Q gain imbalance detection and correction circuit on a slot-by-slot basis based upon the received signal strength.

15. A method as recited in claim 14, wherein the warm-up sequence comprises:

performing a digital offset correction of an I-signal component and a Q-signal component of the received radio frequency signal in a high loop bandwidth mode, thereby producing an unequalized I-signal and an unequalized Q-signal;

equalizing an I/Q gain of the unequalized I-signal and the unequalized Q-signal using a self calibrating PN training signal; and

equalizing an I/Q phase of the unequalized I-signal and the unequalized Q-signal using a self calibrating PN training signal.

16. A method as recited in claim 15 wherein the warm-up sequence occurs after a power on condition of the receiver, and further wherein during the digital offset correction step, the I/Q phase imbalance detection and correction circuit and the I/Q gain imbalance detection and correction circuit are in a reset state.

17. A method as recited in claim 15 wherein the warm-up sequence occurs after a battery save interval of the receiver, and further wherein during the digital offset correction step, the I/Q phase imbalance detection and correction circuit and the I/Q gain imbalance detection and correction circuit are in a hold state.