Context oriented crypto processing on a parallel processor array

• US 20030174843A1
• Filed: 12/05/2002
• Published: 09/18/2003
• Est. Priority Date: 12/05/2001
• Status: Active Grant

• Current Assignee: TecSec, Incorporated
• Original Assignee: TecSec, Incorporated
• Inventors: Wack, C. Jay, Scheidt, Edward, Odell, Mark A.
• Granted Patent: US 7,069,448 B2
• Time in Patent Office: Days
• US Class Current: 380/277
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/06 the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators

Abstract

A system provides cryptographic processing of input data on a parallel processor array that includes plural processors. A format filter extracts control and main data from the input data. A control unit receives the control data, and based on the control data, forwards control and cryptographic parameters to the processors. A first distributor distributes to each processor at least a portion of the main data. A second distributor receives output information from each processor, and based thereon, generates output data. Each processor generates output information based on the control and cryptographic parameters. The output data is a cryptographic processing result.

Claims

1. A system for cryptographic processing of input data on a parallel processor array that includes a plurality of processors, comprising:

a format filter adapted to extract control data and main data from the input data;

a control unit adapted to receive the control data from said format filter, and to forward, based at least in part on the control data, at least one respective control parameter and at least one respective cryptographic parameter to each of the plurality of processors;

a first distributor adapted to receive the main data from said format filter, and to distribute to each of the plurality of processors a respective at least a portion of the main data;

a second distributor adapted to receive respective output information from each of the plurality of processors, and to generate, based at least in part on the respective output information, output data;

wherein each of the plurality of processors is adapted to generate its respective output information based at least in part on the control parameters and the cryptographic parameters, and the output data is a cryptographic processing result.

2. The system of claim 1, wherein said control unit is further adapted to provide state data representative of a state of the processor array.

3. The system of claim 1, wherein the main data is encrypted data and the output data is decrypted data.

4. The system of claim 1, wherein the main data is unencrypted data and the output data is encrypted data.

5. The system of claim 1, wherein each respective at least a portion of the main data is a multiplexed process stream.

6. The system of claim 1, wherein each of the plurality of processors is adapted to initialize based at least in part on the at least one respective control parameter received from the control unit.

7. The system of claim 1, wherein each of the plurality of processors is adapted to perform a cryptographic function based at least in part on the at least one respective cryptographic parameter received from the control unit.

8. The system of claim 1, wherein the at least one respective cryptographic parameter is keying data.

9. The system of claim 1, wherein at least one of the first distributor and the second distributor is a switching matrix.

10. In a system comprising a parallel processor array having a plurality of processors, a method of cryptographically processing input data, comprising:

extracting, from the input data, control data and main data;

forwarding, based at least in part on the control data, at least one respective control parameter and at least one respective cryptographic parameter to each of the plurality of processors;

distributing to each of the plurality of processors a respective at least a portion of the main data;

generating, by each of the plurality of processors, respective output information based at least in part on the at least one respective control parameter and the at least one respective cryptographic parameter; and

generating output data based at least in part on the respective output information;

wherein the output data is a cryptographic processing result.

11. The method of claim 10, further comprising

providing state data representative of a state of the processor array.

12. The method of claim 10, wherein the main data is encrypted data and the output data is decrypted data.

13. The method of claim 10, wherein the main data is unencrypted data and the output data is encrypted data.

14. The method of claim 10, wherein each respective at least a portion of the main data is a multiplexed process stream.

15. The method of claim 10, further comprising

initializing, by each of the plurality of processors, based at least in part on the at least one respective control parameter.

16. The method of claim 10, further comprising

performing, by each of the plurality of processors, a cryptographic function based at least in part on the at least one respective cryptographic parameter.

17. The method of claim 10, wherein the at least one respective cryptographic parameter is keying data.

18. The method of claim 10, wherein at least one of distributing to each of the plurality of processors a respective at least a portion of the main data and generating output data based at least in part on the respective output information is performed by a switching matrix.