Apparatus and method of asynchronous FIFO control
First Claim
1. An apparatus for controlling an asynchronous First-In-First-Out (FIFO) memory comprising an dual port FIFO memory having a read port and a write port for respectively reading out and writing in data at different operation frequencies, a pair of n-bit circular Gray code counters for handshaking read-out and write-in operation frequencies in the dual port FIFO memory and an n-bit overflow binary counter for accumulating overflows of the pair of n-bit circular Gray code counters, wherein n is any integer more than one.
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Abstract
An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write parts of the FIFO, wherein n is any integer more than one. Additional binary counters are used to accumulate the read and write overflows for the circular Gray code counters. When any circular Gray code counter is overflow, the read or write count is transferred to the respective binary counter for recording the FIFO accesses.
22 Citations
12 Claims
- 1. An apparatus for controlling an asynchronous First-In-First-Out (FIFO) memory comprising an dual port FIFO memory having a read port and a write port for respectively reading out and writing in data at different operation frequencies, a pair of n-bit circular Gray code counters for handshaking read-out and write-in operation frequencies in the dual port FIFO memory and an n-bit overflow binary counter for accumulating overflows of the pair of n-bit circular Gray code counters, wherein n is any integer more than one.
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5. An apparatus for controlling an asynchronous First-In-First-Out (FIFO) memory, comprising:
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a write overflow controller, having a write accumulation binary counter with a first input terminal to receive an external write request, a second input terminal, a third input terminal and an output terminal to output a write accumulation signal;
a write handshaking unit, connected to the write overflow controller, having a first synchronizing circuit to receive a write slave signal and output a first synchronous signal to the second input terminal of the write overflow controller, a write master counter with n-bit circular Gray code to receive the first synchronous signal, the external write request and the write accumulation signal and output a write master signal to the third input terminal of the write overflow controller for comparison with the write slave signal to generate the write accumulation signal, a second synchronizing circuit to receive a read master signal and output a second synchronous signal, and a read slave counter with n-bit circular Gray code to receive the second synchronous signal and output a read slave signal;
a write-in FIFO status indicator, including a write pointer having an input terminal to receive the external write request and an outupt terminal to output a write address signal, and a write level pointer having a first input terminal to receive the second synchronous signal from the write handshaking unit, a second input terminal to receive the read slave signal from the write handshaking unit for comparison with the read master signal, a third input terminal to receive the external write request and an output terminal to output an FIFO memory full signal to the external;
an asynchronous dual port FIFO memory, having an input port connected to the write handshaking unit to write in data and an output port to read out data;
a read handshaking unit connected to the output port of the asynchronous dual port FIFO memory, having a third synchronizing circuit to receive the write master signal from the write handshaking unit and output a third synchronous signal, a write slave counter with n-bit circular Gray code to output the write slave signal to the first synchronizing circuit, a read master counter with n-bit circular Gray code having a first input terminal to receive an external read signal, a second input terminal, a first output terminal to output the read master signal to the second synchronizing circuit and a second output terminal, and a fourth synchronizing circuit having an input terminal to receive the read slave signal from the write handshaking unit and an output terminal to output a fourth synchronous signal;
a read overflow controller, having a read accumulation binary counter with a first input terminal to receive the external write request, a second input terminal to receive the fourth synchronous signal, and a third input terminal to receive the read master signal from the read handshaking unit for comparison with the read slave signal from the write handshaking unit and output a read accumulation signal to the second input terminal of the read master counter; and
a read-out FIFO status indicator, including a read pointer having an input terminal to receive the external read request and an outupt terminal to output a read address signal, and a read level pointer having a first input terminal to receive the third synchronous signal from the read handshaking unit, a second input terminal to receive the write slave signal from the read handshaking unit for comparison with the write master signal, and a third input terminal to receive the external read request and an output terminal to output an FIFO memory empty signal to the external. - View Dependent Claims (6)
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7. An operation method, used in an apparatus for controlling an asynchronous First-In-First-Out (FIFO) memory comprising an dual port FIFO memory having a read port for reading out data and a write port for writing in data at different operation frequencies, a pair of n-bit circular Gray code counters for handshaking different read and write operation frequencies in the dual port FIFO memory and an n-bit overflow binary counter for accumulating overflows of the pair of n-bit circular Gray code counters, wherein n is any integer more than one, comprising the steps:
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determining if the pair of n-bit circular Gray code counters have the same value except for zero;
determing the dual port FIFO memory status;
replacing the subsequent operation of the pair of n-bit circular Gray code counters with the n-bit overflow binary counter if the pair of n-bit circular Gray code counters have the same value except for zero and the dual port FIFO memory is not full when an FIFO request comes. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification