Memory read/write reordering

• US 20030177320A1
• Filed: 02/05/2003
• Published: 09/18/2003
• Est. Priority Date: 02/25/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kulick, Stanley S., Sah, Suneeta, Natarajan, Chitra, Pai, Hrishikesh S., Udompanyanan, Varin
• Granted Patent: US 7,047,374 B2
• Time in Patent Office: Days
• US Class Current: 711/158
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/082 Associative directories G06F12/0822 takes precedence
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0862 with prefetch

Abstract

Memory bandwidth may be enhanced by reordering read and write requests to memory. A read queue can hold multiple read requests and a write queue can hold multiple write requests. By examining the contents of the queues, the order in which the read and write requests are presented to memory may be changed to avoid or minimize page replace conflicts, DIMM turn around conflicts, and other types of conflicts that could otherwise impair the efficiency of memory operations.

Claims

1. An apparatus, comprising:

memory to store data;

a request queue to store a request to access the memory;

a re-ordering queue coupled with the request queue to receive more than one request;

an arbitration unit coupled with the re-ordering queue to select requests of the more than one request from the re-ordering queue to process to substantially avoid a conflict in performance of the more than one request.

2. The apparatus of claim 1, further comprising a state machine coupled between the memory and the arbitration unit to perform selected requests of the more than one requests.

3. The apparatus of claim 1, further comprising circuitry coupled with the request queue to respond to a read request based upon a pending write request.

4. The apparatus of claim 1, further comprising a refresh unit to initiate a refresh of a unit of the memory.

5. The apparatus of claim 4, wherein the arbitration unit comprises conflict logic to determine a conflict between the request and the refresh of the unit.

6. The apparatus of claim 1, wherein the re-ordering queue comprises a read reordering queue and a write re-ordering queue.

7. The apparatus of claim 1, wherein the arbitration unit comprises circuitry coupled with the conflict logic to select the request based upon a unit of the memory associated with the request.

8. The apparatus of claim 1, wherein the arbitration unit comprises circuitry coupled with the conflict logic to select the request based upon an availability of a state machine to process the request.

9. The apparatus of claim 1, wherein the arbitration unit comprises circuitry to prioritize the request after re-ordering the request.

10. A system, comprising:

memory to store data associated with a request;

a processor to initiate the request to access the memory; and

a memory controller coupled with the memory to store the request and to re-order the request based upon a conflict with another access to the memory.

11. The system of claim 10, wherein the memory controller comprises a re-order queue to re-order the request.

12. The system of claim 10, wherein the memory controller comprises conflict logic to determine a conflict between the request and another access to the memory.

13. The system of claim 10, wherein the memory controller comprises an arbitration unit to select the request based upon a determination that a state machine is available to process the request.

14. A method, comprising:

storing a first request and a second request in a request queue;

transmitting the requests to a re-ordering queue; and

selecting the second request from the re-ordering queue based upon a conflict between the first request and an access to memory.

15. The method of claim 14, further comprising selecting the first request after the access is substantially completed.

16. The method of claim 14, further comprising responding to a read request in the request queue with data associated with a first request, wherein the first request is a write request.

17. The method of claim 14, wherein said transmitting the requests to a re-ordering queue comprises transmitting the requests based upon an order associated with the requests.

18. The method of claim 14 wherein said selecting the second request comprises selecting the second request based upon availability of a state machine to access the memory associated with the second request.