Integrated circuit security and method therefor

• US 20030177373A1
• Filed: 03/18/2002
• Published: 09/18/2003
• Est. Priority Date: 03/18/2002
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C., Fitzsimmons, Michael D.
• Granted Patent: US 7,266,848 B2
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test

Abstract

The invention relates to an integrated circuit (IC), and more particularly to security to protect an IC (10) against unauthorized accesses. In one embodiment, an identifier is provided external to IC 10. A corresponding input IC security key (52) is then provided to IC 10 and compared to a stored IC security key (30). If the input IC security key (52) and the stored IC security key (30) do not match, access to protected functional circuitry (12) is prohibited. The present invention may use any debug interface, including standard debug interfaces using the JTAG 1149.1 interface defined by the IEEE.

Claims

1. An integrated circuit (IC) comprising:

protected functional circuitry;

storage circuitry for storing a stored IC security key;

an IC debug interface;

comparison circuitry, said comparison circuitry having a first input coupled to the storage circuitry, a second input coupled to the IC debug interface, and an output for providing a protection enable signal; and

access protection circuitry coupled to the protected functional circuitry and having an input to receive the protection enable signal.

2. The IC of claim 1, wherein the comparison circuitry provides the protection enable signal in response to comparing the stored IC security key with an input IC security key received through the IC debug interface.

3. The IC of claim 2, wherein the protected functional circuitry comprises a processor coupled to the access protection circuitry.

4. The IC of claim 2, wherein the protection enable signal has a first state if the stored IC security key and the input IC security key match and a second state if the stored IC security key and the input IC security key do not match.

5. The IC of claim 4, wherein if the protection enable signal has the first state, access protection circuitry allows communication between the IC debug interface and the protected functional circuitry.

6. The IC of claim 4, wherein if the protection enable signal has the second state, access protection circuitry denies communication between the IC debug interface and the protected functional circuitry.

7. The IC of claim 2, further comprising debug circuitry, said debug circuitry comprising:

the access protection circuitry; and

other debug circuitry coupled between the access circuitry and the IC debug interface.

8. The IC of claim 7, wherein portions of the other debug circuitry are disabled in response to the protection enable signal.

9. The IC of claim 7, wherein the other debug circuitry implements a JTAG standard interface.

10. The IC of claim 2, wherein the IC debug interface comprises a plurality of IC debug terminals and the access protection circuitry selectively allows communication between the plurality of IC debug terminals and the protected functional circuitry based on the protection enable signal.

11. The IC of claim 1, wherein the IC debug interface comprises a plurality of IC debug terminals and the access protection circuitry selectively allows communication between the plurality of IC debug terminals and the protected functional circuitry based on the protection enable signal.

12. The IC of claim 11, wherein the IC debug interface is a JTAG interface.

13. The IC of claim 1, further comprising an identifier storage circuitry coupled to the IC debug interface for storing an IC identifier.

14. The IC of claim 13, wherein the IC identifier is provided external to the IC via the IC debug interface.

15. The IC of claim 1, further comprising force enable storage circuitry for storing a force enable value coupled to the comparison circuitry, wherein if the force enable value has a first state, access protection circuitry allows communication between the IC debug interface and the protected functional circuitry, and if the force enable has a second state, access protection circuitry selectively allows communication between the IC debug interface and the protected functional circuitry, based on the protection enable signal.

16. A method for providing security in an IC having protected functional circuitry and at least one IC terminal coupled to the protected functional circuitry, said method comprising:

receiving an input IC security key via the at least one IC terminal;

comparing the input IC security key to a stored IC security key; and

selectively enabling access to the protected functional circuitry via the at least one IC terminal.

17. The method of claim 16, wherein selectively enabling is performed in response to comparing, and comprises:

if the input IC security key and stored IC security key match, enabling access to the protected functional circuitry; and

if the input IC security key and stored IC security key do not match, denying access to the protected functional circuitry.

18. The method of claim 17, further comprising:

if the input IC security key and stored IC security key do not match, waiting a predetermined amount of time prior to comparing a second input IC security key received via the at least one IC terminal to the stored IC security key.

19. The method of claim 17, further comprising:

if the input IC security key and stored IC security key do not match, receiving a second input IC security key via the at least one IC terminal in response to a reset signal.

20. The method of claim 16, wherein if the step of comparing does not result in a match of the input IC security key and stored IC security key within a predetermined window of time, access to the protected functional circuitry is not enabled.

21. The method of claim 16, wherein the at least one IC terminal is a debug terminal.

22. The method of claim 21, wherein the debug terminal is a JTAG terminal.

23. The method of claim 16, further comprising providing an identifier, wherein receiving the input IC security key via the at least one IC terminal is performed in response to providing the identifier.

24. The method of claim 16, wherein the identifier identifies the IC.

25. A method for providing security in an IC having protected functional circuitry and a JTAG interface, said method comprising:

in a first JTAG state, receiving a user defined instruction via the JTAG interface;

in a second JTAG state, receiving an input IC security key via the JTAG input interface, and comparing the input IC security key to a stored IC security key; and

selectively enabling access to the protected functional circuitry via the JTAG interface.

26. The method of claim 25, wherein the first JTAG state corresponds to a SHIFT_IR state.

27. The method of claim 26, wherein the second JTAG state corresponds to a SHIFT_DR state.

28. The method of claim 25, further comprising:

in a third JTAG state, loading an instruction register with the user defined instruction; and

in the second JTAG state, executing the user defined instruction.

29. The method of claim 28, wherein the first JTAG state corresponds to a SHIFT_IR state, the second JTAG state corresponds to a SHIFT_DR state, and the third JTAG state corresponds to a UPDATE_IR state.

30. The method of claim 25, further comprising:

in a third JTAG state, providing an identifier via the JTAG interface.

31. The method of claim 30, wherein the first JTAG state corresponds to a SHIFT_IR state, the second JTAG state corresponds to a SHIFT_DR state, and the third JTAG state corresponds to the SHIFT_IR state.

32. A method for providing security in an IC having protected functional circuitry and at least one IC terminal coupled to the protected functional circuitry, said method comprising:

accessing the protected functional circuitry via the at least one IC terminal;

programming a force enable indicator to enable comparison circuitry, wherein the comparison circuitry compares an input IC security key to a stored IC security key and, in response to comparing, selectively enables access to the protected functional circuitry via the at least one IC terminal.

33. The method of claim 32, wherein the force enable indicator comprises a fuse.

34. The method of claim 33, wherein programming the force enable indicator comprises blowing the fuse.