Stacked spacer structure and process

• US 20030178688A1
• Filed: 03/22/2002
• Published: 09/25/2003
• Est. Priority Date: 03/22/2002
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Yang, Shih-Hsien, Chuang, Yueh-Cheng, Sheu, Bor-Ru
• Granted Patent: US 6,828,219 B2
• Time in Patent Office: Days
• US Class Current: 257/395
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A stacked spacer structure and process adapted for a stacked layer on a semiconductor substrate is described. The stacked spacer structure is formed on the sidewalls of the stacked layer which comprising a conductive layer and a cap layer thereon. A dielectric layer made of a material with low dielectric constant lower than that of silicon nitride is formed on the semiconductor substrate. A first silicon nitride layer is then formed over the substrate. The first silicon nitride layer and dielectric layer are etched sequentially to form an inner spacer on the sidewalls of the stacked layer. A second silicon nitride layer is formed over the substrate, and etched to form an outer spacer on the sidewalls of the inner spacer. By forming the stacked spacer structure of the present invention embedded low dielectric material, the coupling capacitance produced therein will be greatly reduced.

Claims

1. A method of fabricating a stacked spacer structure, comprising the steps of:

providing a semiconductor substrate having a stacked layer, said stacked layer comprising a conductive layer and a cap layer thereon;

forming a dielectric layer substantially higher than said conductive layer on said semiconductor substrate;

forming a first silicon nitride layer over said semiconductor substrate;

etching said first silicon nitride layer and said dielectric layer sequentially to form a first spacer on the sidewalls of said stacked layer;

forming a second silicon nitride layer over said semiconductor substrate; and

etching said second silicon nitride layer to form a second spacer on the sidewalls of said first spacer.

2. The method according to claim 1, wherein said cap layer comprises a silicon nitride layer.

3. The method according to claim 1, wherein said dielectric layer is made of a low dielectric material having a dielectric constant lower than that of silicon nitride.

4. The method according to claim 3, wherein said dielectric layer comprises a silicon oxide layer.

5. The method according to claim 1, further comprising forming a thin silicon nitride layer on the sidewalls of said stacked layer before forming said dielectric layer.

6. The method according to claim 1, wherein said stacked layer comprises a word line.

7. The method according to claim 6, further comprising a gate dielectric layer between said semiconductor substrate and said conductive layer.

8. The method according to claim 6, wherein said conductive layer comprises a polysilicon layer and a tungsten layer.

9. The method according to claim 1, wherein said stacked layer comprises a bit line.

10. The method according to claim 9, wherein a material of said conductive layer is selected from the group consisting of polysilicon, aluminum, tungsten, copper and a combination thereof.

11. The method according to claim 9, further comprising forming a contact hole adjacent to said first spacer after forming said first spacer.

12. The method according to claim 11, wherein said second spacer is extended to the sidewalls of said contact hole.

13. A method of fabricating a semiconductor structure, comprising the steps of:

forming a stacked layer comprising a conductive layer and a first dielectric layer thereon on a semiconductor substrate;

forming a second dielectric layer substantially higher than said conductive layer on said semiconductor substrate;

forming a third dielectric layer over said semiconductor substrate;

etching said third dielectric layer and said second dielectric layer sequentially to form a first spacer on the sidewalls of said stacked layer;

forming a fourth dielectric layer over said semiconductor substrate; and

etching said fourth dielectric layer to form a second spacer on the sidewalls of said first spacer.

14. The method according to claim 13, wherein said first and third dielectric layers have high respective etching selectivities to said second dielectric layer.

15. The method according to claim 13, wherein a material of said first, third and fourth dielectric layers comprises silicon nitride.

16. The method according to claim 13, wherein said second dielectric layer has a dielectric constant lower than that of said first, third and fourth dielectric layers.

17. The method according to claim 16, wherein said second dielectric layer comprises a silicon oxide layer.

18. The method according to claim 13, further comprising forming a thin liner layer on the sidewalls of said stacked layer after forming said stacked layer.

19. The method according to claim 18, wherein a material of said liner layer comprises silicon nitride.

20. The method according to claim 13, wherein said stacked layer comprises a word line.

21. The method according to claim 20, further comprising a gate dielectric layer between said semiconductor substrate and said conductive layer.

22. The method according to claim 13, wherein said stacked layer comprises a bit line.

23. The method according to claim 22, further comprising forming a contact hole adjacent to said first spacer after forming said first spacer.

24. The method according to claim 23, wherein said second spacer is extended to the sidewalls of said contact hole.

25. A stacked spacer structure located on the sidewalls of a stacked layer on a semiconductor substrate, said stacked layer including a conductive layer and a cap layer thereon, comprising:

a low dielectric bottom portion substantially higher than said conductive layer on said semiconductor substrate and on the sidewalls of said stacked layer;

a silicon nitride top portion on said low dielectric bottom portion and on the sidewalls of said stacked layer, said silicon nitride top portion and said low dielectric bottom layer constructing an inner spacer; and

an outer portion on the sidewalls of said low dielectric bottom portion and said silicon nitride top portion.

26. The structure according to claim 25, wherein said low dielectric bottom portion is made of a low dielectric material having a dielectric constant lower than that of silicon nitride.

27. The structure according to claim 26, wherein a material of said low dielectric bottom portion comprises silicon oxide.

28. The structure according to claim 27, further comprising a thin silicon nitride liner layer on the sidewalls of said stacked layer between inside said low dielectric bottom portion and said silicon nitride top portion.

29. The structure according to claim 25, wherein said stacked layer comprises a word line.

30. The structure according to claim 29, further comprising a gate dielectric layer between said semiconductor substrate and said conductive layer.

31. The structure according to claim 25, wherein said stacked layer comprises a bit line.

32. The structure according to claim 31, wherein said semiconductor substrate further comprises a contact hole adjacent to said first spacer.

33. The structure according to claim 32, wherein said second spacer is extended to the sidewalls of said contact hole.

34. A semiconductor structure formed on a semiconductor substrate, comprising:

a stacked layer formed on the semiconductor substrate, said stacked layer comprising a conductive layer and a first dielectric layer thereon;

a second dielectric layer substantially higher than said conductive layer on said semiconductor substrate and on the sidewalls of said stacked layer;

a third dielectric layer on said second dielectric layer and on the sidewalls of said stacked layer, said second dielectric layer and said third dielectric layer constructing an inner spacer; and

a fourth layer on the sidewalls of said second and third dielectric layers.

35. The structure according to claim 34, wherein said first and third dielectric layers have high respective etching selectivities to said second dielectric layer.

36. The structure according to claim 34, wherein a material of said first, third and fourth dielectric layers comprises silicon nitride.

37. The structure according to claim 34, wherein said second dielectric layer has a dielectric constant lower than that of said first, third and fourth dielectric layers.

38. The structure according to claim 37, wherein said second dielectric layer comprises a silicon oxide layer.

39. The structure according to claim 34, further comprises a thin liner layer on the sidewalls of said stacked layer.

40. The structure according to claim 39, wherein a material of said liner layer comprises silicon nitride.

41. The structure according to claim 34, wherein said stacked layer comprises a word line.

42. The structure according to claim 41, further comprising a gate dielectric layer between said semiconductor substrate and said conductive layer.

43. The structure according to claim 34, wherein said stacked layer comprises a bit line.

44. The structure according to claim 34, wherein said semiconductor substrate further comprises a contact hole adjacent to said inner spacer.

45. The structure according to claim 44, wherein said outer spacer is extended to the sidewalls of said contact hole.