Reduced terminal testing system

• US 20030178692A1
• Filed: 03/17/2003
• Published: 09/25/2003
• Est. Priority Date: 09/13/1996
• Status: Active Grant

• Current Assignee: Eugene H. Cloud, Leland R. Nevill, Raymond J. Beffa, Warren M. Farnworth
• Original Assignee: Eugene H. Cloud, Leland R. Nevill, Raymond J. Beffa, Warren M. Farnworth
• Inventors: Beffa, Raymond J., Farnworth, Warren M., Cloud, Eugene H., Nevill, Leland R.
• Granted Patent: US 6,852,999 B2
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2841 Signal generators
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2868 Complete testing stations; systems; procedures; software aspects
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die. A wafer mode controlling system includes a system controller to control application of the alternating signals and other signals to the dice on the wafer. The semiconductor wafer mode controlling system may also control a probe positioning controller including an array of probes that selectively brings the probes into contact with the probe pads, whereby the alternating signal having the certain characteristics is transmitted from the probe to the circuitry through the probe pad and conductive path and the circuitry of each of the dice is placed into the mode.

Claims

1. A semiconductor wafer having substrate as a portion thereof comprising:

a plurality of dice located on portions of the substrate, the plurality of dice including circuitry for placing at least one die of the plurality of dice into a mode upon receipt of an alternating signal having a predetermined characteristic by the circuitry, said mode selected from one of a predetermined testing mode for testing a plurality of dice, a functional test mode, and a parametric test mode, the alternating signal selected from one of a test pattern signal and information in a signal form and

a conductive path connected to the circuitry providing the alternating signal to the circuitry.

2. The wafer of claim 1, wherein said alternating signal further comprises a plurality of test patterns for said plurality of dice.

3. The wafer of claim 1, wherein said alternating signal further comprises a plurality of information for said plurality of dice.