Direct conversion receiver

• US 20030179837A1
• Filed: 03/13/2003
• Published: 09/25/2003
• Est. Priority Date: 03/25/2002
• Status: Active Grant

• Current Assignee: Hitachi Kokusai Electric Incorporated (Hitachi, Ltd.)
• Original Assignee: Hitachi Kokusai Electric Incorporated (Hitachi, Ltd.)
• Inventors: Akaike, Kazuo, Nakamura, Manabu, Takahashi, Kazushi, Ide, Teruji
• Granted Patent: US 7,218,685 B2
• Time in Patent Office: Days
• US Class Current: 375/324
• CPC Class Codes: H04L 27/1525 using quadrature demodulation

Abstract

To solve such a problem of a conventional direct conversion receiver that an image rejection ratio is insufficient owing to analog processing employed to reject an image, the present invention provides such a direct conversion receiver that the image can be rejected by digital signal processing to improve the image rejection ratio and also reduce the hardware load and the processing load. A HILBERT filter of a digital signal processing section shifts a quadrature component digital signal by 90° by HILBERT conversion to provide an output, while a delay circuit delays an in-phase component digital signal by the same delay time as a delay time by the HILBERT filter to provide an output, both of which outputs undergo addition or subtraction at an adder to have the image rejected there and then enter a complex frequency converter, where an offset provided at a local oscillator is removed by frequency conversion processing to output the in-phase component and quadrature component signals.

Claims

1. A direct conversion receiver which comprises:

a local oscillator which oscillates a carrier wave at a reception frequency plus an offset;

a first multiplier which multiplies a reception signal by an output of the local oscillator;

a first low pass filter which rejects a double wave from an output of the first multiplier;

a first AD converter which converts an output of the first low pass filter into a digital signal to provide an in-phase component of the digital signal;

a 90°

phase shifter which shifts the output of the local oscillator by 90°

;

a second multiplier which multiplies the reception signal by an output of the 90°

phase shifter;

a second low pass filter which reject the double wave from an output of the second multiplier;

a second AD converter which converts an output of the second low pass filter into the digital signal to provide a quadrature component of the digital signal; and

a digital signal processing section which performs processing for receiving the in-phase component of the digital signal and the quadrature component of the digital signal to reject an image frequency signal contained in these received signals and which performs frequency conversion processing for removing the offset provided at the local oscillator.

2. The direct conversion receiver according to claim 1, wherein the digital signal processing section comprises:

a 90°

phase shifter which receives the quadrature component of the digital signal output from the second AD converter and which performs 90°

phase shift processing;

a delay circuit which receives the in-phase component of the digital signal output from the first AD converter to output it with the same delay time as a delay time in the 90°

phase shifter; and

an adder which performs addition or subtraction between an output of the 90°

phase shifter and an output of the delay circuit.

3. The direct conversion receiver according to claim 1, wherein the 90°

phase shifter is a HILBERT filter which performs 90°

phase shift processing by HILBERT conversion.

4. The direct conversion receiver according to claim 3, wherein the HILBERT filter comprises:

an odd number of the delay circuits for outputting an input signal while delaying the input signal, the delay circuits being connected in series and divided into a front-stage group and a rear-stage group symmetrically with respect to the central one of the odd number of the delay circuits;

a plurality of adders which performs subtraction between the input signals of the delay circuits of the front-stage group and the output signals of the delay circuits of the rear-stage group disposed symmetrically with each other;

an adder which performs subtraction between the input and output signals of the central delay circuit;

a plurality of multipliers which multiplies the output signal of each of the adders by a filter coefficient; and

an adder which adds up the outputs of the plurality of multipliers.

5. The direct conversion receiver according to claim 4, wherein the plurality of multipliers in the HILBERT filter does not perform the multiplication when the filter coefficient for the multiplication is 0.

6. The direct conversion receiver according to claim 1, wherein the digital signal processing section comprises:

a complex frequency converter which performs frequency conversion processing for removing an offset provided at the local oscillator for signal from which the image frequency signal is removed, thereby outputting the in-phase component and quadrature component signals; and

a low pass filter which gives a band limit to each of the in-phase component and quadrature-component signals sent from the complex frequency converter.

7. The direct conversion receiver according to claim 6, wherein the complex frequency converter comprises:

a first SIN table and a first COS table which are set beforehand to perform frequency conversion processing for rejecting the offset provided at the local oscillator;

a first multiplier which multiplies an input signal by a value in the first SIN table to output an in-phase component signal; and

a second multiplier which multiplies the input signal by a value in the first COS table to output a quadrature component signal.

8. The direct conversion receiver according to claim 7, wherein the complex frequency converter comprises:

a second SIN table and a second COS table which are set beforehand to perform frequency conversion processing for rejecting a minute frequency offset;

a third multiplier which multiplies the in-phase component signal from the first multiplier by a value in the second SIN table;

a fourth multiplier which multiplies the in-phase component signal from the first multiplier by a value of the second COS table;

a fifth multiplier which multiplies the quadrature component signal from the second multiplier by the value in the second COS table;

a sixth multiplier which multiplies the quadrature component signal from the second multiplier by the value of the second SIN table;

a subtractor which subtracts the output of the third multiplier and the output of the fifth multiplier; and

an adder which adds up the output of the fourth multiplier and the output of the sixth multiplier.