Method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof

• US 20030181053A1
• Filed: 03/19/2003
• Published: 09/25/2003
• Est. Priority Date: 03/20/2002
• Status: Abandoned Application

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hwang, Paul-Ling, Lu, Wen-Pin, Chiu, Hung-Yu, Tseng, U-Way
• Application Number:
  US10/390,690
• Publication Number:
  US 20030181053A1
• Time in Patent Office: Days
• US Class Current: 438/694
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof. A gate structure is formed on a substrate. Diffusion regions are formed in the substrate on either side of the gate structure. A linear oxide layer is formed on the gate structure and the substrate. A conformal nitride layer is formed on the linear oxide layer. The nitride layer and the linear oxide layer are partially etched back to form linear oxide spacers on the sides of the gate structure and nitride spacers on the sides of the linear oxide spacers. A conformal oxide layer is formed on the linear oxide spacers, the nitride spacers, the gate structure and the substrate. The oxide layer is partially etched back to form oxide spacers on the sides of the nitride spacers.

Claims

1. A method of manufacturing a nonvolatile memory cell, comprising:

providing a substrate;

forming at least one gate structure on the substrate;

forming diffusion regions in the substrate on either side of the gate structure;

forming a conformal linear oxide layer on the gate structure and the substrate;

forming a conformal nitride layer on the linear oxide layer;

anisotropically etching the nitride layer and the linear oxide layer to expose a partial surface of the substrate and the top surface of the gate structure, thereby forming linear oxide spacers on the sides of the gate structure and nitride spacers on the sides of the linear oxide spacers;

forming a conformal oxide layer on the linear oxide spacers, the nitride spacers, the gate structure and the substrate; and

anisotropically etching the oxide layer to expose a partial surface of the substrate and the top surface of the gate structure, thereby forming oxide spacers on the sides of the nitride spacers;

wherein, mobile ions are blocked from approaching the gate structure by means of the nitride spacers.

2. The method according to claim 1, further comprising the step of:

forming a dielectric layer on the oxide spacers, the gate structure and the substrate.

3. The method according to claim 1, wherein the method of forming the gate structure comprises the steps of:

forming a tunnel oxide layer on part of the substrate;

forming a floating gate on the tunnel oxide layer;

forming an inter-gate dielectric layer on the floating gate; and

forming a control gate on the inter-gate dielectric layer.

4. The method according to claim 1, wherein the linear oxide layer is a silicon oxide layer formed by thermal oxidation.

5. The method according to claim 1, wherein the linear oxide layer is about 50˜

250 angstroms.

6. The method according to claim 1, wherein the nitride layer is a silicon nitride layer formed by deposition.

7. The method according to claim 1, wherein the nitride layer is a silicon oxynitride layer formed by deposition.

8. The method according to claim 1, wherein the nitride layer is about 100˜

300 angstroms.

9. The method according to claim 1, wherein the oxide layer is a silicon oxide layer formed by deposition.

10. The method according to claim 1, wherein the oxide layer is about 2000˜

3000 angstroms.

11. A nonvolatile memory cell structure, comprising:

a substrate having a gate structure;

linear oxide spacers formed on the sides of the gate structure;

nitride spacers formed on the sides of the linear oxide spacers;

oxide spacers formed on the sides of the nitride spacers; and

diffusion regions formed in the substrate on either side of the gate structure;

wherein, mobile ions are blocked from approaching the gate structure by means of the nitride spacers.

12. The structure according to claim 11, wherein the structure further comprises:

a dielectric layer formed on the oxide spacers, the gate structure and the substrate.

13. The structure according to claim 11, wherein the gate structure comprises:

a tunnel oxide layer formed on part of the substrate;

a floating gate formed on the tunnel oxide layer;

an inter-gate dielectric layer formed on the floating gate; and

a control gate formed on the inter-gate dielectric layer.

14. The structure according to claim 11, wherein the linear oxide spacer comprises silicon oxide.

15. The structure according to claim 11, wherein the linear oxide spacer is about 50˜

250 angstroms.

16. The structure according to claim 11, wherein the nitride spacer comprises silicon nitride.

17. The structure according to claim 11, wherein the nitride spacer comprises silicon oxynitride.

18. The structure according to claim 11, wherein the nitride spacer is about 100˜

300 angstroms.

19. The structure according to claim 11, wherein the oxide spacer comprises silicon oxide.

20. The structure according to claim 11, wherein the oxide spacer is about 2000˜

3000 angstroms.