Analog power detection for gain control operations

• US 20030181179A1
• Filed: 05/03/2002
• Published: 09/25/2003
• Est. Priority Date: 03/25/2002
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Darabi, Hooman
• Granted Patent: US 7,013,117 B2
• Time in Patent Office: Days
• US Class Current: 455/234.1
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes

Abstract

A method and apparatus for dynamically controlling a programmable gain amplifier (PGA) in a radio receiver to provide a plurality of gain steps thereby providing automatic gain control (AGC) in a receiver intermediate frequency (IF) stage comprises an analogy peak detector formed to including a constant current source and a plurality of MOSFETs all configured to produce an output voltage (DC) whose value reflects a peak amplitude of a received differential quadrature phase shift keyed (QPSK) signal. A first circuit portion generates currents that are proportional to the square of the magnitude of the gate to source voltage for each of a plurality of MOSFETs coupled to receive the differential QPSK signal and a second circuit portion produces a voltage that is equal to the square root of the sum of the squares of the currents produced (drawn) by the MOSFETs of the first circuit portion.

Claims

1. A radio receiver formed in an integrated circuit, comprising:

a low noise amplifier (LNA) coupled to receive a radio frequency (RF) signal from an antenna;

a pair of mixers coupled to receive an output of the LNA, the mixers for down converting the received RF signal to baseband;

a pair of filters for receiving down converted signals from the mixers;

logic circuitry for providing gain level control signals;

at least one programmable gain amplifier (PGA) for providing controlled gain steps according to the gain level control signals received from the logic circuitry; and

an analog peak detection circuit coupled to receive filtered I and Q baseband signals from the filters having an output voltage characterized by a square root of the sum of the squares of the magnitude of the I and Q components.

2. The radio receiver of claim 1 wherein the analog peak detection circuit further comprising four inputs to receive one of each of four signal components of a quadrature phase shift keyed communication signal.

3. The radio receiver of claim 2 further comprising at least four amplification components, each of the amplification components coupled to one of each of the four signal inputs, the four amplification components for producing a current whose magnitude is a function of the square of the signal magnitude of the signal components.

4. The radio receiver of claim 3 further including output circuitry for generating a constant DC current and a fluctuating current component wherein the DC current and fluctuating current components are equal to the currents generated by the sum of the four amplification components, the output circuitry coupled to the amplification components through a single node.

5. The radio receiver of claim 4 wherein the output circuitry contains two amplifiers for producing an output voltage that is proportional to the fluctuating components.

6. The radio receiver of claim 5 wherein the output voltage is proportional to the magnitude of the I and Q components of the received signal.

7. A radio receiver formed in an integrated circuit, comprising:

a low noise amplifier (LNA) coupled to receive a radio frequency (RF) signal from an antenna;

a mixer coupled to receive an output of the LNA, the mixer for down converting the received RF signal to baseband;

at least one programmable gain amplifier (PGA) for providing controlled gain steps according to received control signals; and

analog peak detection circuitry whose output voltage further including;

a first circuit portion for squaring the magnitude of four quadrature signals;

a second circuit portion coupled to the first circuit portion for summing each of the squared signals and for providing a square root of the current driven by the first circuit portion; and

logic circuitry coupled to receive a peak voltage component from the analog peak detection circuit, the logic circuitry for generating the control signals to the PGA.

8. The radio receiver of claim 7 wherein the first circuit portion includes at least four matched MOSFETs each coupled in parallel to receive one of the four quadrature signals, the first matched MOSFET receiving a signal characterized by the equation V_BIAS+(a)sin(ω

t).

9. The radio receiver of claim 8 wherein the first circuit portion includes at least four matched MOSFETs each coupled in parallel to receive one of the four quadrature signals, the second matched MOSFET receiving a signal characterized by the equation V_BIAS−

(a)sin((ω

t).

10. The radio receiver of claim 9 wherein the first circuit portion includes at least four matched MOSFETs each coupled in parallel to receive one of the four quadrature signals, the third matched MOSFET receiving a signal characterized by the equation V_BIAS+(a)cos(ω

t).

11. The radio receiver of claim 10 wherein the first circuit portion includes at least four matched MOSFETs each coupled in parallel to receive one of the four quadrature signals, the fourth matched MOSFET receiving a signal characterized by the equation V_BIAS−

(a)cos(ω

t).

12. The radio receiver of claim 11 wherein the first circuit portion includes a node coupled to the drain of each of the at least four matched MOSFETs, the node further coupled to receive a current from a current source.

13. The radio receiver of claim 12 wherein the drain is further coupled to receive current from at least two matched MOSFETs coupled in parallel, the pair of MOSFETs being coupled in parallel to the current source.

14. The radio receiver of claim 12 wherein the at least two matched MOSFETs each have a gate terminal coupled to V_DD.

15. The radio receiver of claim 14 wherein the node conducts a current that is equal to I_DC+Bet(a)a².

16. The radio receiver of claim 15 wherein the node is further coupled to the output of the analog peak detection circuitry and provides an output that is equal to V_DD−

V_GS−

a, wherein, functionally, the output is equal to the square root of the sum of the squares of the magnitude of each of the signal components of the quadrature input signals.

17. A radio receiver, comprising:

transceiver circuitry for transmitting and receiving communication signals for communicating using phase shift keyed modulation circuitry;

programmable gain amplifier circuitry for receiving differential phase shift keyed modulation signals from the transceiver circuitry, and analog peak detection circuit further comprising;

a first circuit portion, the first circuit portion further including a first plurality of MOSFETs, each having a gate terminal coupled to receive a differential modulated signal component;

a second circuit portion, the second circuit portion further including a second plurality of

MOSFETs, each having a gate terminal coupled to V_DD, the second circuit portion further including a current source for providing a specified constant current.

18. The radio receiver of claim 17 wherein the first plurality of MOSFETs comprises a number of MOSFETs that is equal to a multiple of four.

19. The radio receiver of claim 17 wherein the second plurality of MOSFETs comprises a number of MOSFETs for conducting fluctuating signals that is equal to one half of the number of MOSFETs in the first plurality of MOSFETS for conducting fluctuating signals.

20. A method in a radio receiver formed within an integrated circuit for adjusting a gain level of a programmable gain amplifier, comprising:

receiving a differential modulated signal at each of a first plurality of MOSFETs;

biasing each of the MOSFETS of the first plurality of MOSFETs into a saturation region;

producing a current at each of the first plurality of MOSFETs that is equal to a function of the square of the gate to source voltage;

summing the currents produced by the first plurality of MOSFETs to draw a current;

producing, in a current source, a constant amount of current into a node coupled to the drains of the first plurality of MOSFETs; and

producing, in a second plurality of MOSFETs whose gate terminals are coupled to a supply voltage to place the second plurality of MOSFETs in a saturation mode of operation, an amount of current that is equal to a device constant (Beta) times the square of the amplitude of the phase modulated signals received at the gate terminals of the first plurality of MOSFETs.

21. The method of claim 20 further including the step of producing an output voltage at the node that is equal to a peak value of the amplitude of the phase modulated signals received at the first plurality of MOSFETs.