Derating factor determination for integrated circuit logic design tools

• US 20030182098A1
• Filed: 02/05/2003
• Published: 09/25/2003
• Est. Priority Date: 05/03/1999
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Ehrler, Timothy J.
• Granted Patent: US 7,010,475 B2
• Time in Patent Office: Days
• US Class Current: 703/19
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An integrated circuit development library is provided that characterizes several different logic device cells. The library specifies a number of different timing relationships for each of the logic device cells. These timing relationships are evaluated for each of the logic device cells at a first derating condition with a first simulator to provide a first set of derated condition values. The first set of derated condition values each correspond to one of the timing relationships evaluated. A first derating factor is calculated from the first set of derated condition values for estimating derated performance of an integrated circuit with a second simulator. This integrated circuit is developed from one or more of the logic device cells of the library.

Claims

1. A method, comprising:

(a) providing an integrated circuit development library characterizing several different logic device cells, the library specifying a number of different timing relationships for each of the logic device cells;

(b) evaluating each of the different timing relationships for each of the logic device cells at a first derating condition with a first simulator to provide a first set of derated condition values, the first set of derated condition values each corresponding to one of the timing relationships evaluated; and

(c) calculating a first derating factor from the first set of derated condition values for estimating derated performance of an integrated circuit with a second simulator, the integrated circuit being developed with one or more of the logic device cells of the library.

2. The method of claim 1, wherein the first derating condition corresponds to one of temperature, voltage, or process.

3. The method of claim 1, further comprising evaluating each of the timing relationships for each of the logic device cells at a second derating condition different than the first derating condition with the first simulator to provide a second set of derated condition values.

4. The method of claim 3, wherein the first set of derating condition values and the second set of derating condition values respectively correspond to best and worst case conditions.

5. The method of claim 3, wherein said calculating includes:

determining a first calculated value from the first set of derated condition values and a second calculated value from the second set of derated condition values; and

deriving the first derating factor from the first and second calculated values.

6. The method of claim 3, wherein the first derating factor corresponds to a best or worst case kfactor.

7. The method of claim 1, further comprising determining a number of derating factors for the second simulator, the derating factors each corresponding to a unique combination of one of a number of timing relationship types and one of a number of deration parameters, the deration parameters each corresponding to one of process, voltage, or temperature.

8. A method, comprising:

(a) providing an integrated circuit development library including a plurality of different logic device cell characterizations, the library specifying a number of timing relationships for each of the logic device cell characterizations, the timing relationships each being one of a predetermined number of different timing relationship types;

(b) determining a set of derating values from a subset of the timing relationships and a derating condition parameter, each member of the subset being of the same timing relationship type;

(c) performing said determining for each of the different cell timing relationship types to provide a number of different sets of derating values, each of the different sets of derating values being determined from a different subset of the timing relationships; and

(d) calculating a plurality of derating factors to estimate derated performance of an integrated circuit developed from one or more of the different logic device cell characterizations, the derating factors each being representative of a different one of the timing relationship types and each being determined from a corresponding one of the different sets of derating values.

9. The method of claim 8, wherein a first group of the timing relationship types correspond to transition time and propagation time.

10. The method of claim 9, wherein a second group of the timing relationship types correspond to setup time and hold time.

11. The method of claim 8, wherein said determining and said performing include evaluating each of the timing relationships with a first simulation tool, and the derating factors are each adapted for estimating derated performance of the integrated circuit with a second simulation tool.

12. The method of claim 8, wherein the derated condition parameter corresponds to one of temperature, voltage, or process.

13. The method of claim 12, wherein the timing relationships number at least 1000 more than the plurality of derating factors.

14. The method of claim 13, wherein the derating factors include a first subset corresponding to process deration, a second subset corresponding to voltage deration, a third subset corresponding to temperature deration, and each of the first, second, and third subsets include at least one factor corresponding to propagation delay and at least one factor corresponding to transition delay.

15. The method of claim 8, wherein said calculating includes determining a number of multiplier arrays for each of the derating factors and screening each of the arrays for anomalous entries.

16. An apparatus, comprising:

a processing system including;

means for providing a library including a plurality of logic device cell descriptions each including a number of timing relationships;

means for determining a number of derating values for characterizing derated performance of each of the logic device cells, each of the derating values being determined by evaluating a different one of the timing relationships for each of the logic device cell descriptions at a derating condition with a first simulator; and

means for calculating a number of derating factors, the derating factors each being determined from a different subset of the derating values, the derating factors being applicable to estimate derated performance of an integrated circuit developed from the library with a second simulator.

17. The apparatus of claim 16, wherein said providing means includes a computer readable medium encoded with said library.

18. The apparatus of claim 16, wherein said calculating means includes a processor operable to execute a derating factor extraction program to calculate said derating factors.

19. The apparatus of claim 18, wherein said calculating means includes means for establishing a number of best case multiplier arrays and a number of worst case multiplier arrays.

20. The apparatus of claim 18, wherein said calculating means includes means for screening each of the best case multiplier arrays and each of the worst case multiplier arrays.

21. An apparatus, comprising:

a computer readable medium, the medium defining an integrated circuit development library including;

a characterization of each of a number of different logic device cells, the library specifying a number of timing relationships for each of the cells, the timing relationships each being one of several different timing relationship types;

a set of derating factors to estimate derated performance of an integrated circuit developed from one or more of the logic device cells, the derating factors each corresponding to a unique combination of one of the timing relationship types and one of a number of derating conditions, the derating factors each being determined in accordance with an evaluation of each of the timing relationships that belong to a corresponding one of the timing relationship types at a corresponding one of the derating conditions for each of the different logic device cells of the library; and

wherein the derating conditions each correspond to deration of one of process, temperature, or voltage.

22. The apparatus of claim 21, wherein the derating factors number at least 30.

23. The apparatus of claim 22, wherein a first group of 10 of the derating factors correspond to process derating, a second group of 10 of the derating factors correspond to voltage derating, and a third group of 10 of the derating factors correspond to temperature derating.

24. The apparatus of claim 21, wherein the derating factors are each determined as a function of timing at extremes of a derating range for the corresponding one of the timing relationship types for each of the different logic device cells characterized by the library.