(Design rule check)/(electrical rule check) algorithms using a system resolution

• US 20030182644A1
• Filed: 03/21/2002
• Published: 09/25/2003
• Est. Priority Date: 03/21/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Li, Mu-Jing, Yang, Amy
• Granted Patent: US 6,735,749 B2
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Method and apparatus for checking integrated circuit designs. In particular, one embodiment of the present invention is a method that for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of: (a) growing one or more rectangular boxes having at least two sides of length equal to the system resolution outward or inward from one or more of an edge of a design object and a side of a design object; (b) performing one or more of a spacing DRC/ERC check and an overlay DRC/ERC check; and (c) identifying checks relating to the rectangular boxes.

Claims

1. A method for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of:

growing one or more rectangular boxes having at least two sides of length equal to the system resolution outward or inward from one or more of an edge of a design object and a side of a design object;

performing one or more of a spacing DRC/ERC check and an overlay DRC/ERC check; and

identifying checks relating to the rectangular boxes.

2. The method of claim 1 wherein the system resolution is equal to one-tenth of a grid spacing.

3. The method of claim wherein at least one of the rectangular boxes has four sides of length equal to the system resolution.

4. A method for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of:

determining an amount equal to one-half of a predetermined width less the system resolution;

decreasing a dimension of each side of design objects by the amount;

increasing a dimension of each side of the design objects by the amount; and

identifying narrow design objects as those that have disappeared.

5. A method for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of:

determining a first amount equal to a predetermined amount plus the system resolution;

determining a second amount equal to the predetermined amount less the system resolution; and

identifying a length of an edge or side of a design object when the length is less than the first amount and greater than the second amount.

6. A method for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of:

selecting design objects having an edge equal to a predetermined length;

growing a rectangular box having two sides of length equal to the system resolution inside the edge;

performing an enclosure operation; and

identifying errors generated by the rectangular boxes.

7. A method for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of:

growing rectangular boxes having at least two sides of length equal to the system resolution outward from sides of a polysilicon design object associated with MOS design objects;

performing an overlap check between the rectangular boxes and a source design object and a drain design object associated with the MOS design objects; and

identifying a partial gate whenever the rectangular box does not overlap the source design object or the drain design object.

8. A method for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of:

growing rectangular boxes having at least two sides of length equal to the system resolution outward from edges of a polysilicon design object associated with MOS design objects;

performing an overlap check between the rectangular boxes and a source design object and a drain design object associated with the MOS design objects; and

identifying a partial gate whenever a rectangular box overlaps the source design object or the drain design object.

9. A method for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of:

growing rectangular boxes having at four sides of length equal to the system resolution outward from vertices of rectangular design objects;

performing an overlap check between the rectangular boxes and the rectangular design objects; and

identifying a notch whenever an overlap occurs between an edge of a rectangular box and an edge of a rectangular design object.

10. A method for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of:

growing rectangular boxes having at least two sides of length equal to the system resolution inward from an end of design objects;

performing a spacing check between the ends and sides of design objects; and

identifying a spacing check between ends of two design objects by spacing checks involving rectangular boxes.

11. A computer readable medium containing (design rule check)/(electrical rule check) files (DRC/ERC files) for checking integrated circuit design files wherein design objects are disposed on a grid having a system resolution, the computer readable medium comprising:

program instructions for growing one or more rectangular boxes having at least two sides of length equal to the system resolution outward or inward from one or more of an edge of a design object and a side of a design object;

program instructions for performing one or more of a spacing DRC/ERC check and an overlay DRC/ERC check; and

program instructions for identifying checks relating to the rectangular boxes.

12. An apparatus for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files), the apparatus comprising:

means for growing one or more rectangular boxes having at least two sides of length equal to the system resolution outward or inward from one or more of an edge of a design object and a side of a design object;

means for performing one or more of a spacing DRC/ERC check and an overlay DRC/ERC check; and

means for identifying checks relating to the rectangular boxes.