CMOS imager for pointing and tracking applications
First Claim
1. An integrated semiconductor device comprising:
- an active pixel sensor array;
a diagonal switch array coupled with the active pixel sensor array;
a memory array coupled with the diagonal switch array;
a readout block coupled with the memory array; and
a controller configurable to operate the diagonal switch array, the memory array, and the readout block in a tracking mode to read out two or more windows in the active pixel sensor array.
2 Assignments
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Accused Products
Abstract
Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.
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Citations
40 Claims
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1. An integrated semiconductor device comprising:
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an active pixel sensor array;
a diagonal switch array coupled with the active pixel sensor array;
a memory array coupled with the diagonal switch array;
a readout block coupled with the memory array; and
a controller configurable to operate the diagonal switch array, the memory array, and the readout block in a tracking mode to read out two or more windows in the active pixel sensor array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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sampling multiple rows and multiple columns of an active pixel sensor array into an on-chip analog memory array; and
reading out the multiple rows and multiple columns sampled in the on-chip memory array to provide image data with reduced motion artifact. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. An imaging system comprising:
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an active pixel sensor array;
a memory array coupled with the active pixel sensor array;
a readout block coupled with the memory array; and
a controller configurable to operate the memory array, and the readout block in multiple modes, including a first mode employing a sample-first-read-later readout scheme. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. An integrated semiconductor device comprising:
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an active pixel sensor array;
a memory array coupled with the active pixel sensor array;
a readout block coupled with the memory array; and
a controller configurable to operate the memory array and the readout block to perform four-point correlated double sampling. - View Dependent Claims (37, 38, 39, 40)
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Specification